Configurable Switch Network for Sorted Array Intersection
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Solution Overview
Problem
Existing parallel computing systems face performance degradation due to synchronization challenges when intersecting sorted arrays across multiple cores, leading to increased latency and reduced efficiency in operations like graph analytics and database applications.
Innovation Solution
The implementation of a scalable system using a network of configurable switches with specific ISA instructions and hardware modifications to support sorted array intersection operations, reducing software complexity and enhancing performance by managing the intersection operation within the switch hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel computing is used to intersect sorted arrays, then computation speed is improved, but synchronization overhead increases and performance degrades
Solution Approach 1:
The patent divides the parallel computing system into multiple independent processing cores that operate on different segments of the array intersection problem simultaneously. Each core processes a portion of the input arrays independently, eliminating the need for frequent synchronization between cores and reducing synchronization overhead while maintaining high computation speed.
2Productivity
If hardware parallelization is used for array intersection, then processing efficiency is improved, but synchronization complexity increases
Solution Approach 1:
The patent extracts the synchronization logic from the core processing units and implements it in dedicated hardware circuitry. This separates the complex synchronization functions from the simple computation units, allowing multiple cores to operate in parallel with reduced synchronization complexity while maintaining high processing efficiency.
3Device complexity
If a single core pipeline is used for array intersection, then synchronization is simplified, but performance is degraded
Solution Approach 1:
The patent merges multiple simple processing pipelines into a unified parallel architecture where each pipeline processes a segment of the data independently. By combining these simple pipelines with a coordinated output stage, the system achieves high performance while keeping individual pipeline complexity low and synchronization manageable.
Data Source
AI summary
Techniques for multi-dimensional network sorted array intersection. A first switch of a plurality of switches of an apparatus may receive a first element of a first array from a first compute tile of the plurality of compute tiles and a first element of a second array from a second compute tile of the plurality of compute tiles. The first switch may determine that the first element of the first array is equal to the first element of the second array. The first switch may cause the first element of the first array to be stored as a first element of an output array, the output array to comprise an intersection of the first array and the second array.