Precharge Logic Gate Balancing Against Side-Channel Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for protecting sensitive data in microcircuit devices against attacks like SPA, DPA, and EMA are inadequate, as they still allow for information leaks through statistical imbalances in logic gate switchings, which can be exploited by attackers.
Innovation Solution
A countermeasure method that involves adapting logic gates during a precharge phase to ensure binary output probabilities match random input data, using precharge control signals to transform statistically unbalanced gates into balanced or inverting gates, and employing multiplexers and transistor configurations to maintain output randomness regardless of input data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a precharge phase with random binary data is provided to the logic circuit, then the logic gates are triggered to switch randomly, but statistical imbalances in unbalanced logic gates (AND, OR, NAND, NOR) still cause information leakage through variations in current consumption and electromagnetic radiation
Solution Approach 1:
The logic gate is transformed into a dynamically reconfigurable structure that can switch between different operational modes (balanced and unbalanced) based on control signals. During the precharge phase, the gate is configured to operate in balanced mode where all inputs are forced to the same logic level, ensuring equal probability of output states. During the processing phase, the gate operates in unbalanced mode to perform its logical function. This dynamic reconfiguration eliminates statistical imbalances during precharge while maintaining functional correctness during processing.
Solution Approach 2:
The invention changes the operational parameters of the logic gate by introducing control signals that modify the gate's behavior. Specifically, control signals force certain inputs to fixed logic levels (0 or 1) during the precharge phase, transforming the gate from its normal logical operation to a balanced state where output probability is 0.5 regardless of random input data. This parameter change ensures that no statistical information about the random data is leaked through power consumption or electromagnetic radiation patterns.
2Reliability
If all inputs of unbalanced logic gates are forced to the same logic level during precharge phase, then the gate becomes statistically balanced, but additional control signals and multiplexers are required increasing circuit complexity
Solution Approach 1:
The invention makes the logic gate universal by enabling it to perform multiple functions: normal logical operation during the processing phase and balanced statistical operation during the precharge phase. By integrating control signal logic and multiplexer functionality directly into the gate structure, the same physical gate handles both modes of operation without requiring separate dedicated circuits for each function, thereby reducing overall system complexity.
Solution Approach 2:
The control logic for forcing inputs to fixed levels is merged with the existing logic gate structure rather than being implemented as separate external circuits. The multiplexers that select between forced and normal input modes are integrated into the gate's input stage, combining the precharge control functionality with the logical operation functionality in a unified structure, thus minimizing additional complexity.
3Loss of information
If control signals are used to transform logic gates into balanced or inverting gates, then output probabilities match random input data, but more control infrastructure is needed
Solution Approach 1:
The control signals operate in a periodic manner, alternating between precharge phase (where inputs are forced to fixed levels) and processing phase (where normal logical operation occurs). This periodic switching is synchronized with the overall circuit operation timeline, allowing the same control infrastructure to serve multiple gates throughout the system by applying control signals in coordinated time intervals, thereby reducing the total control signal requirements.
Data Source
Figure 1~3A
Figure 3B~4B
Figure 5~6
AI summary
The method involves supplying data to process the inputs (A1-A4) of a logic circuit during a data processing phase, and supplying a precharge command signal (P) launching a precharge phase on input of the logic circuit. The functioning of logic gates (AG1, AG2, OG1, OG2) e.g. AND, NAND, OR, or NOR type gate, of a statistically unbalanced logic circuit is adopted, so that the output signal of the logic gate is in a binary state with a same probability as the random binary data supplied on input of the logic circuit during the precharge phase. An independent claim is also included for a device for a countermeasure method for a logic circuit to protect sensitive data processed in an electronic component of a portable device comprising a multiplexer.