Precision Pulse Generator Circuit Without Delay-Chain Power Loss
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Solution Overview
Problem
Conventional pulse generators, particularly those using delay chains, are inefficient in terms of power consumption and vulnerable to race-through failures due to pulse width variations, which detract from the efficiency of pulse flops in modern semiconductor designs.
Innovation Solution
The economy precision pulse generating circuit incorporates a pre-charge circuit, a gate-to-the-partial-jam-latch-keeper circuit, a partial-jam-latch-keeper circuit, and a pull-down-against-the-up-keeper circuit, utilizing a logical AND circuit with a source clock signal and a common storage node to produce output pulses with adjustable widths, reducing power consumption and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a delay chain is used in conventional pulse generators, then pulse width can be controlled, but power consumption increases significantly
Solution Approach 1:
The pulse generation function is segmented into multiple specialized circuits: pre-charge circuit, gate-to-partial-jam-latch-keeper circuit, partial-jam-latch-keeper circuit, and pull-down-against-up-keeper circuit. Each circuit performs a specific function in the pulse generation sequence, replacing the continuous operation of delay chains with discrete, controlled switching events that consume power only when needed.
Solution Approach 2:
The circuit uses periodic clock signals to trigger pre-charge and discharge operations at specific intervals. The pre-charge circuit operates periodically to reset the storage node, while the pull-down circuit operates periodically to generate the pulse, replacing the continuous power consumption of delay chains with periodic, event-driven operation.
2Productivity
If delay chain switches twice per clock cycle, then pulse generation is achieved, but active power consumption increases
Solution Approach 1:
The invention extracts the essential pulse generation function from the delay chain architecture. By taking out only the necessary timing and switching functions and implementing them through specialized circuits (pre-charge, gate-to-partial-jam-latch-keeper, pull-down-against-up-keeper), the design eliminates the excessive power consumption inherent in full delay chain operation while maintaining pulse generation capability.
Solution Approach 2:
The circuit changes the operational parameters from continuous delay chain switching to event-driven circuit switching triggered by clock edges. The storage node voltage transitions are controlled by specific circuit events rather than continuous delay line operation, reducing the frequency and duration of active power consumption while maintaining the required pulse generation timing.
3Adaptability or versatility
If pulse width varies, then timing flexibility is improved, but race-through failure vulnerability increases
Solution Approach 1:
The circuit employs feedback mechanisms where the output pulse feeds back to control the pull-down-against-up-keeper circuit. This feedback ensures that the pulse generation is tightly coupled with the actual circuit state, preventing premature or extended pulse widths that could cause race-through failures while maintaining the ability to adjust timing through controlled feedback delay.
Solution Approach 2:
The pre-charge circuit provides beforehand cushioning by ensuring the storage node is properly charged before each potential pulse event. This pre-conditioning creates a safety margin that prevents race-through failures by ensuring adequate voltage levels are established before the pulse generation sequence begins, cushioning against timing variations.
Data Source
AI summary
A system includes an input device, an output device, a mechanical chassis, a printed circuit board, and a semiconductor device. The semiconductor device includes a mechanical package, and a semiconductor die. The semiconductor die includes a semiconductor layer, a plurality of metal layers, a clock distribution network that distributes a clock signal within the die, and an economy precision pulse generating circuit. The economy precision pulse generating circuit includes a pre-charge circuit, a gate-to-the-partial-jam-latch-keeper circuit, a partial-jam-latch-keeper circuit, and a pull-down-against-the-up-keeper circuit. A source clock signal is derived from the clock signal. The source clock signal is provided to a first input of a logical AND circuit, the pre-charge circuit, and the gate-to-the-partial-jam-latch-keeper circuit. A common storage node is connected to a second input of the logical AND circuit. The logical AND circuit outputs an output pulse. The output pulse is fed back to the pull-down-against-the-up-keeper circuit.