Predicted Error Correction for Memory Read Failures
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Solution Overview
Problem
Current memory systems face limitations in error correction capabilities, which compromise data reliability and processing efficiency during read operations due to the trade-off between error correction and system performance.
Innovation Solution
A predicted error correction technique that identifies data likely to cause read failures, generates predicted error parity, and stores indexes to correct errors proactively, enhancing the memory system's ability to manage and correct errors during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction capability is enhanced to improve data reliability, then read failure correction improves, but system performance deteriorates due to increased processing overhead
Solution Approach 1:
The patent applies preliminary action by generating predicted error parity data before actual read operations occur. The controller proactively identifies data likely to cause read failures and pre-generates parity information, so that when read failures actually occur, correction can be performed quickly using the pre-prepared parity data rather than performing complex error correction calculations in real-time during read operations.
Solution Approach 2:
The patent segments the error correction process into two distinct phases: a background preparation phase where predicted error parity is generated for data likely to fail, and a read phase where this pre-generated parity is used for rapid correction. This segmentation allows the system to perform thorough error correction preparation without blocking normal read operations, thus maintaining system performance while improving data reliability.
2Reliability
If comprehensive error correction is performed on all data, then read failure correction improves, but processing time increases
Solution Approach 1:
The patent applies local quality by selectively applying error correction resources only to data that is locally identified as being at high risk of read failure. Instead of uniformly processing all data, the controller analyzes data characteristics and generates predicted error parity only for specific data segments that meet failure risk criteria, thereby reducing overall processing time while maintaining high correction capability for vulnerable data.
Solution Approach 2:
The patent implements partial action by performing error correction preparation on only a subset of data - specifically those identified as likely to cause read failures - rather than performing comprehensive error correction on all stored data. This selective approach reduces processing time while still providing robust error correction where it is most needed.
3Reliability
If error correction resources are allocated to improve data reliability, then read failure handling improves, but system efficiency deteriorates
Solution Approach 1:
The patent applies self-service by enabling the memory system to automatically identify which data requires error correction resources and allocate them accordingly. The controller autonomously analyzes data characteristics, determines failure risk, and directs error correction processing only where necessary, eliminating the need for external resource allocation mechanisms and improving overall system efficiency while maintaining high error correction capability.
Solution Approach 2:
The patent changes the parameter of resource allocation from static (uniform allocation to all data) to dynamic (adaptive allocation based on data characteristics and failure risk). By adjusting error correction resource allocation based on varying data parameters such as age, access patterns, and error susceptibility, the system optimizes both reliability and efficiency simultaneously.
Data Source
AI summary
A memory system may include: a memory device configured to perform one or more of data write, read and erase operations; and a controller configured to execute an error management command and control the operation of the memory device, wherein the error management command is configured to determine first data which is highly likely to cause a read fail, among data stored in the memory device, determine one or more second data which is used to generate predicted error parity, and generate the predicted error parity based on the determined first and second data, and wherein the memory device performs the write operation to store indexes of the first and second data and the predicted error parity, under control of the controller.