Prediction Unit Pipeline for Microprocessor Fetch Latency
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Solution Overview
Problem
The lengthy instruction fetch process in processors is due to the sequential nature of address translation, instruction cache way determination, and data readout steps, which involve significant memory access times and contribute to pipeline latency, especially in high-frequency designs, and branch mispredictions lead to idle execution units and performance penalties.
Innovation Solution
A microprocessor with a prediction unit pipeline that includes stages for making predictions based on fetch addresses and branch history, allowing for parallel access to instruction cache and translation lookaside buffer, reducing the instruction fetch pipeline length and latency, and dynamically folding or unfolding the pipeline in response to misses or mispredictions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If sequential address translation, cache way determination, and data readout steps are used, then memory access is simplified, but instruction fetch time increases significantly
Solution Approach 1:
The patent performs address translation and cache way determination in advance before the actual data readout is needed. Specifically, the set index is used to pre-determine the cache way in parallel with other fetch operations, so that when data readout is required, the path is already established, eliminating sequential delays
Solution Approach 2:
The patent introduces parallelism by operating in multiple dimensions simultaneously - address translation, cache way determination, and data readout all occur in parallel rather than sequentially. This is achieved by using the set index to independently determine cache ways while simultaneously performing translation and readout operations
2Speed
If a long instruction fetch pipeline is implemented, then high processor clock frequency is achieved, but branch misprediction latency increases
Solution Approach 1:
The patent performs address translation and cache way determination in advance before they are actually needed for data readout. By pre-computing these values in parallel with fetch operations, the pipeline depth is reduced, allowing shorter pipeline stages that can operate at higher frequencies while reducing the penalty when mispredictions occur
Solution Approach 2:
The patent dynamically adjusts the pipeline structure by folding or unfolding stages based on operational needs. The ability to perform operations in parallel and restructure the pipeline dynamically allows optimization for both high clock frequency operation and reduced misprediction latency
3Loss of time
If parallel access to instruction cache and translation lookaside buffer is implemented, then instruction fetch latency is reduced, but device complexity increases
Solution Approach 1:
The patent segments the instruction fetch process into distinct parallel stages - address translation, cache way determination, and data readout - each handling a specific subtask. This segmentation allows independent parallel execution of each stage while maintaining overall process simplicity through clear separation of functions
Solution Approach 2:
The prediction unit pipeline is designed to perform multiple functions simultaneously - it handles both address translation and cache way determination in parallel, making it a multi-functional unit that reduces overall system complexity despite the parallel operations it performs
Data Source
AI summary
A microprocessor includes a prediction unit pipeline having a first stage that makes first predictions at a rate of one per clock cycle. Each first prediction comprises a hash of a fetch address of a current fetch block and branch history update information produced by a previous fetch block immediately preceding the current fetch block. Second one or more stages, following the first stage, with a latency of N (at least one) clock cycles, use the first predictions to make second predictions at a rate of one per clock cycle. Each second prediction includes a fetch address of a next fetch block immediately succeeding the current fetch block and branch history update information produced by the current fetch block. For each second prediction of the second predictions, logic uses the second prediction to check whether the first prediction made N−1 clock cycles earlier than the second prediction is a mis-prediction.