Predictive Time-to-Digital Converter With Segmented Delay Line
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Solution Overview
Problem
Current digital transceiver architectures face challenges in achieving high resolution and low power consumption for time-to-digital converters (TDCs) used in phase-locked loops and digital-to-time converters (DTCs), which are essential for modern radios, particularly in LTE standards, as existing TDCs are either large or power-hungry.
Innovation Solution
The implementation of a TDC with a mix of coarse and fine delay elements, a multiplexer, and a latch circuit allows for precise time measurement while reducing the number of delay elements and power consumption, enabling smaller and more energy-efficient designs that maintain high resolution, and includes a recycle path to extend measurement range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional TDC designs are used to achieve high resolution time measurement, then measurement precision is improved, but chip area and power consumption increase
Solution Approach 1:
The delay line is segmented into multiple stages with different numbers of delay elements, where earlier stages have more elements and later stages have fewer elements. This segmentation allows the TDC to achieve high resolution for short time intervals while using fewer total elements, thereby reducing chip area while maintaining measurement precision.
Solution Approach 2:
The TDC dynamically adjusts the number of active delay elements based on the predicted time interval of the input signal. By using a multiplexer to selectively enable delay elements in different stages, the system adapts the delay line configuration to match the expected measurement range, optimizing both resolution and area utilization.
2Measurement precision
If traditional TDC designs are used to achieve high resolution time measurement, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The delay line is divided into multiple stages with varying numbers of delay elements. By activating only the necessary stages based on prediction information, the system reduces the total number of active delay elements, thereby lowering dynamic power consumption while maintaining the required time measurement resolution.
Solution Approach 2:
Prediction information is used beforehand to determine which delay elements need to be activated. This preliminary action allows the TDC to pre-configure the delay line to match the expected time interval, avoiding the activation of unnecessary delay elements and reducing overall power consumption.
3Area of stationary object
If the number of delay elements is reduced to decrease chip area, then area is improved, but measurement precision deteriorates
Solution Approach 1:
The delay line is segmented into multiple stages where each stage contributes differently to the total resolution. Earlier stages provide coarse measurement with fewer elements, while later stages provide fine measurement. This segmentation allows the system to achieve high overall resolution with fewer total elements compared to a uniform delay line design.
Solution Approach 2:
Different stages of the delay line have different local qualities in terms of resolution contribution. The system assigns more delay elements to stages that require finer resolution and fewer elements to stages with coarser resolution requirements, optimizing the distribution of elements to achieve high precision with minimal area.
4Productivity
If prediction information is used to route signals selectively, then productivity is improved, but device complexity increases
Solution Approach 1:
Prediction information is obtained in advance to determine the appropriate delay line configuration before the actual measurement occurs. This preliminary action allows the multiplexer to pre-select and activate only the necessary delay elements, speeding up the measurement process by avoiding full delay line activation while adding only minimal complexity through the multiplexer control logic.
Data Source
AI summary
Predictive time-to-digital converters (TDCs) and methods for providing a digital representation of a time interval are disclosed herein. In an example, a TDC can include a delay line, a selection circuit, and a latch circuit. The delay line can include a plurality of delay elements configured to propagate a first edge of a first signal sequentially through the plurality of delay elements. The selection circuit can be configured to receive the first signal, to receive prediction information, and to route the first signal to an input of one of the plurality of delay elements based on the prediction information. The latch circuit can receive a second signal and can latch a plurality of outputs of the delay line upon reception of a second edge of the second signal. An output of the latch circuit can provide an indication of a delay between the first edge and the second edge.