Press Pack Cell Chip Assemblage With Segmented Control Electrodes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional press pack cells experience significant voltage drops across pressure contact pieces during operation, leading to temporal switching delays in semiconductor switches due to differing control voltages at individual semiconductor chips.
Innovation Solution
A chip assemblage is created with a control electrode interconnection structure and a main electrode interconnection structure, using a dielectric embedding compound to connect semiconductor chips, along with dedicated compensation laminae to manage mechanical and thermal stresses, and a method for operating a press pack cell that maintains a consistent drive voltage across all chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If semiconductor chips are pressed between two electrically conductive pressure contact pieces and electrically connected in parallel, then the electrical connection is simplified, but significant voltage drops occur during operation causing temporal switching delays
Solution Approach 1:
The invention segments the electrical connection path by introducing separate control electrode connections for each semiconductor chip. Instead of a single parallel connection through pressure contact pieces, each chip receives its control voltage through an individual control electrode, dividing the current path and eliminating the voltage drop problem that affects switched-on time.
Solution Approach 2:
The invention introduces control electrodes as intermediary elements between the power supply and the semiconductor chips. These control electrodes serve as dedicated mediators for control voltage transmission, separate from the main current-carrying pressure contact pieces, thereby preventing the voltage drop in the main contacts from affecting the control signal timing.
2Power
If a strong electric current flows via the pressure contact piece during operation, then the main current conduction is ensured, but a voltage drop occurs causing control voltage differences at individual chips
Solution Approach 1:
The electrical connection system is segmented into two independent pathways: one for main current conduction through pressure contact pieces, and another for control voltage delivery through dedicated control electrodes. This segmentation allows the high current path to be optimized for power transmission while the control path maintains voltage consistency without being affected by the main current's voltage drop.
Solution Approach 2:
The control electrodes are designed to maintain equipotential conditions at each semiconductor chip's control terminal. By providing direct, low-impedance control electrode connections to each chip, the invention ensures that all control points remain at the same reference potential despite the voltage drop occurring in the separate main current conduction path through pressure contact pieces.
Data Source
AI summary
One aspect of the invention relates to a chip assemblage. The latter comprises a number of semiconductor chips, each of which has a semiconductor body having an underside, and also a top side, which is spaced apart from the underside in a vertical direction. A top main electrode is arranged on the top side and a bottom main electrode is arranged on the underside. Moreover, each of the semiconductor chips has a control electrode, by means of which an electric current between the top main electrode and the bottom main electrode can be controlled. The semiconductor chips are connected to one another by a dielectric embedding compound to form a solid assemblage. The chip assemblage additionally comprises a common control terminal, and a common reference potential terminal. The common control terminal is electrically conductively connected to each of the control electrodes via a control electrode interconnection structure, and the common reference potential terminal is electrically conductively connected to each of the first main electrodes via a main electrode interconnection structure. Moreover, a dedicated, electrically conductive top compensation lamina is present for each of the semiconductor chips, said top compensation lamina being arranged on that side of the top main electrode which faces away from the semiconductor body and being cohesively and electrically conductively connected to the top main electrode.