PRF-Based Secure BIST for SoC Side-Channel Protection
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Solution Overview
Problem
Traditional BIST methods in Systems-on-Chip (SoC) are vulnerable to side-channel attacks and incur high area and latency overheads due to the use of simple pseudorandom generators and cryptographic algorithms like AES, making them inefficient for secure test pattern generation and hashing.
Innovation Solution
Implement lightweight cryptography-based BIST using Pseudo-Random Functions (PRF) for secure test pattern generation and hashing, achieving low latency and high security with 128-bit strength by performing multiple round computations in a single cycle and precomputing round constants in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional BIST uses simple pseudorandom generators like LFSR, then the implementation is simple and area is small, but the system becomes vulnerable to side-channel attacks and lacks security
Solution Approach 1:
The patent changes the fundamental parameters of the test pattern generator by replacing simple LFSR with PRF-based generation. The PRF takes a seed key and counter as inputs and produces secure test patterns through cryptographic functions, fundamentally altering how test patterns are generated to achieve security while maintaining reasonable complexity
Solution Approach 2:
The patent introduces a PRF-based test pattern generator as an intermediary component between the seed key and the test patterns. This intermediary uses cryptographic primitives to transform simple inputs into secure test patterns, providing security without requiring complex direct implementations
2Reliability
If cryptographic algorithms like AES are used for secure test pattern generation, then security is improved, but latency and area overhead increase significantly
Solution Approach 1:
The patent segments the cryptographic operation into smaller components: a PRF that processes data in rounds, where each round operates on smaller data blocks. This segmentation allows the system to achieve cryptographic security through multiple simple operations rather than a single complex AES operation, reducing latency
Solution Approach 2:
The patent uses a PRF that performs fewer cryptographic rounds than full AES but achieves sufficient security strength. By using partial action (fewer rounds) with a different cryptographic approach (PRF instead of block cipher), the system achieves adequate security with reduced latency
3Reliability
If cryptographic algorithms like AES are used for secure test pattern generation, then security is improved, but area overhead increases making BIST infeasible
Solution Approach 1:
The patent uses a PRF that can be implemented with relatively simple hardware logic compared to full AES. The PRF uses basic logic gates and registers to perform cryptographic functions, creating a 'cheap' implementation that provides sufficient security without the expensive area overhead of full AES hardware
4Productivity
If traditional BIST is used, then implementation is simple and fast, but functional correctness cannot be securely demonstrated at power-on
Solution Approach 1:
The patent implements a feedback mechanism where the test pattern generator uses the output of the circuit under test to update the internal state. This feedback allows the system to verify functional correctness by checking whether the circuit produces expected responses to the secure test patterns, maintaining speed while enabling secure verification
Data Source
AI summary
Techniques for secure built in self test are described. Some examples include a secure test pattern generator to generate a secure test pattern using a pseudo-random function (PRF) circuitry; a scan out hash engine to hash a scan out of a circuit to be tested; and a comparison circuit to compare the hashed scan out to a known value to verify the hash.