Programmable Priority Encoder Circuit With Reduced Timing Depth
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Solution Overview
Problem
Conventional programmable priority encoders face challenges with long timing paths and circular combinational loops, leading to high delays and difficulties in operating at high clock speeds, especially for moderate values of N-bits.
Innovation Solution
The implementation of low-depth programmable priority encoders and circular programmable priority encoders using efficient circuit designs that reduce propagation delay and Boolean logic gate count, employing techniques such as segmentation, modular operations, and reorganization of AND-OR chains into trees, allowing for faster operation without increasing gate count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a ripple carry implementation is used in conventional programmable priority encoders, then the encoder can be implemented with straightforward circuitry, but the timing path becomes long causing 2N-3 Boolean gate delay
Solution Approach 1:
The encoder circuit is divided into multiple independent stages or segments that process different portions of the priority encoding simultaneously. This segmentation breaks the long sequential ripple carry path into parallel segments, reducing the critical path delay while maintaining the encoding functionality through coordinated stage outputs.
Solution Approach 2:
The circuit architecture transitions from a one-dimensional sequential ripple carry structure to a multi-dimensional parallel structure. By organizing the encoding logic across multiple dimensions (stages, blocks, or hierarchical levels), the design achieves simultaneous processing of multiple input bits, reducing the Boolean gate delay from 2N-3 to a constant or logarithmic value.
2Productivity
If the encoder operates at high clock speeds, then productivity increases, but the long timing path causes difficulty in achieving stable operation
Solution Approach 1:
By segmenting the encoder into multiple stages with controlled output timing, each stage can be optimized to meet specific timing requirements. This allows the overall circuit to operate at high clock speeds while maintaining stability through synchronized stage transitions and proper timing closure.
Solution Approach 2:
The circuit performs preliminary processing in earlier stages that prepares data for subsequent stages, allowing the critical path to be optimized for high-speed operation. Intermediate results are computed and stabilized before being passed to the next stage, ensuring reliable operation at high clock frequencies.
3Device complexity
If conventional encoder designs are used, then the gate count and fanout remain moderate, but the propagation delay becomes excessive for high-speed applications
Solution Approach 1:
The encoding function is segmented into multiple parallel processing paths, each handling a subset of inputs. This reduces the fanout requirement for individual gates while maintaining moderate overall gate count, as the segmentation allows reuse of logic across stages and eliminates the need for large fanout gates that would increase delay.
Solution Approach 2:
The circuit architecture reorganizes the logic from a flat structure with high fanout requirements to a hierarchical or multi-layer structure. This dimensional transformation allows the same encoding function to be achieved with lower fanout per gate and moderate gate count, while the parallel nature of the new structure reduces propagation delay significantly.
Data Source
AI summary
An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.