Probabilistic Erase Method for NAND Flash Memory Endurance

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Solution Overview

Problem

NAND flash memory devices face challenges in endurance and retention due to the destructive nature of block erase operations, which reduce the number of program/erase cycles and data storage reliability, especially with multi-level cell configurations.

Innovation Solution

A method of probabilistic erase is employed, where not all memory cells in a block need to be erased completely, with a predetermined percentage of successful erasures determining the completion of the erase operation, and error correction coding is used to handle stuck cells, reducing the intensity and time of erase operations and increasing the number of program/erase cycles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a block erase operation is performed to clear memory cells, then data storage reliability is improved, but the number of program/erase cycles decreases

Engineering Contradiction:
Improvedata storage reliabilityVSAvoidnumber of program/erase cycles
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent applies partial erase action by determining whether all memory cells in a block are actually erased before deciding to perform another erase operation. Instead of performing full block erase operations unconditionally, the system tests individual cells and only re-erases blocks that contain unerased cells, thereby reducing unnecessary erase cycles and extending memory device endurance while maintaining data reliability.

Inventive Principle:
Principle #16Partial or excessive action

2Reliability

If a block erase operation is performed with high negative voltage, then erased state is achieved, but channel insulating films are damaged

Engineering Contradiction:
Improveerased stateVSAvoiddamage to channel insulating films
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent implements feedback control by testing memory cells after erase operations to determine their actual erased state. Based on test results showing whether cells are properly erased, the system decides whether to perform additional erase operations. This feedback mechanism prevents excessive erase operations that would cause cumulative damage to channel insulating films while ensuring cells achieve the required erased state for reliable data storage.

Inventive Principle:
Principle #23Feedback

3Reliability

If all memory cells are required to be erased completely, then data integrity is improved, but erase time increases

Engineering Contradiction:
Improvedata integrityVSAvoiderase time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial verification action by testing a subset of memory cells or using statistical methods to determine block erase completion rather than verifying every single cell. The system determines that a block is sufficiently erased when a predetermined percentage of tested cells meet the erased state criteria, allowing faster erase operations while maintaining adequate data integrity through error correction coding to handle any remaining stuck cells.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9105339B2Methods of driving a memory
Publication Date: 2015.08.11 SAMSUNG ELECTRONICS CO LTD
  • US9105339B2 patent drawing
  • US9105339B2 patent drawing
  • US9105339B2 patent drawing

AI summary

Methods of driving a memory include erasing a plurality of memory cells of a memory device, testing whether the memory cells have been erased, and programming the memory cells without erasing the memory cells again if more than a predetermined percentage of the memory cells, but less than all of the memory cells, were successfully erased.