Probe Card Signal Switch IC for Hierarchical Channel Control
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Solution Overview
Problem
Current probe cards face increased channel control time due to extreme miniaturization of semiconductor processes, necessitating a large number of switch ICs, which hampers throughput.
Innovation Solution
A switch IC with a hierarchical control system that includes a command decoder and selector to transmit switch IC, core, and channel selection data in one frame, enabling rapid activation of multiple channels through parallel data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large number of switch ICs are mounted on the probe card to support extreme miniaturization and high multiplexing, then the measurement channel capacity is improved, but the channel control time increases and throughput deteriorates
Solution Approach 1:
The control system is segmented into hierarchical levels: probe card controller, switch IC, core, and channel. Each level manages specific subsets of channels, allowing parallel control operations. The command decoder at each level independently processes control signals for its designated channels, enabling simultaneous control of multiple channels without sequential delays.
Solution Approach 2:
The patent introduces a hierarchical control structure that adds a dimensional layer to channel management. Instead of flat sequential control, the system organizes channels through multiple levels of abstraction (probe card → switch IC → core → channel), enabling parallel processing across different hierarchical dimensions and reducing overall control time.
2Quantity of substance
If multiple switch ICs are mounted on the probe card to handle increased measurement channels, then channel capacity is improved, but device complexity increases
Solution Approach 1:
Each switch IC is designed as a universal module capable of handling multiple cores and channels through standardized interfaces. The command decoder and selector structures are replicated across switch ICs with identical functionality, allowing interchangeable deployment and simplifying system integration despite the increased number of components.
Solution Approach 2:
The patent implements a nested hierarchical structure where channels are grouped under cores, cores are grouped under switch ICs, and switch ICs are mounted on the probe card. This nesting organizes complexity into manageable layers, with each level managing a subset of the total system, making the overall complex structure more controllable and maintainable.
3Loss of time
If hierarchical control commands are implemented to rapidly activate multiple channels, then channel setup time is reduced, but command processing complexity increases
Solution Approach 1:
The command decoder is pre-configured with decoding tables and logic structures that map hierarchical command codes to specific channel activation patterns. Common control operations are pre-programmed into the decoder, allowing rapid execution without real-time computation, thus reducing channel setup time while managing processing complexity through predetermined logic.
Data Source
AI summary
A switch IC includes a plurality of cores, each of the cores including a plurality of channels, each of the channels being connected to a device under test (DUT), a command decoder configured to receive an identifier (ID) and a command, decode the ID and the command, and form a control signal for control of the cores and the channels, and a selector configured to provide a signal for control of activation of the cores and the channels to correspond to the control signal output by the command decoder, wherein the command includes switch IC selection data, OP CODE, core selection data, and channel selection data in one frame, and is a command encoded to hierarchically control the plurality of cores and the plurality of channels.