2D Processor Array Edge Interconnection for Area Reduction
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Solution Overview
Problem
Existing multiple-core processors face challenges in reducing interconnection area and power consumption while meeting the complex requirements of various applications, particularly in reconfigurable computing environments.
Innovation Solution
A processor array with a two-dimensional arrangement of processing elements, featuring shared processing elements at edges and peripherally arranged load and store units, which reduces interconnection area and power consumption by implementing partial interconnections optimized for specific algorithms like FIR, IIR, FFT, and beamforming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If full interconnection is implemented to enable PE interconnection solutions, then computing capability and parallel processing are improved, but interconnection area and power consumption increase significantly
Solution Approach 1:
The processor array is segmented into multiple processing elements (PEs) arranged in a two-dimensional grid structure with edge rows and columns. This segmentation allows for localized interconnections between adjacent PEs rather than full interconnection, reducing the overall interconnection area while maintaining parallel processing capability through the structured grid layout and shared edge PEs.
Solution Approach 2:
The patent transitions from a conventional one-dimensional or fully interconnected two-dimensional layout to a structured two-dimensional grid with explicit edge rows and columns. This dimensional organization enables data flow to propagate through the array in structured patterns, reducing the need for direct interconnections between all PE pairs while maintaining computational efficiency.
2Adaptability or versatility
If full interconnection is implemented to support reconfigurable computing, then adaptability for various algorithms is improved, but power consumption increases
Solution Approach 1:
The processing elements on the edges (edge row PEs and edge column PEs) serve multiple functions: they act as regular computation PEs for internal operations and simultaneously function as interface points for external data input and output. This multi-functionality reduces the need for separate dedicated interface PEs, lowering overall power consumption while maintaining versatility for various algorithms including FIR, IIR, FFT, and beamforming.
Solution Approach 2:
The patent applies different interconnection characteristics to different regions of the processor array. Edge PEs have enhanced connectivity for external communication, while internal PEs use simplified local interconnections. This localized differentiation optimizes power consumption by providing high adaptability only where needed at the boundaries, while reducing power usage in the bulk computation region.
3Area of stationary object
If edge PEs are shared between rows and columns to reduce interconnection area, then interconnection complexity is reduced, but data flow management becomes more complex
Solution Approach 1:
The shared edge PEs dynamically switch between their dual roles based on the computational requirements of the active algorithm. The interconnection network can reconfigure data flow paths through these edge PEs to accommodate different algorithmic needs, such as row-major or column-major data access patterns, without requiring physical reconfiguration of the hardware structure.
Data Source
AI summary
The present disclosure provides a processor array and a multiple-core processor. The processor array includes a plurality of processing elements arranged in a two-dimensional array, a plurality of first load units correspondingly arranged and connected to the processing elements of the first edge row, respectively, a plurality of second load units correspondingly arranged and connected to the processing elements of the first edge column, respectively, a plurality of first store units correspondingly arranged and connected to the processing elements of the second edge column, respectively, a plurality of second store units correspondingly arranged and connected to the processing elements of the second edge row, respectively.