Processor Power Control via Micro-Architectural Bandwidth Throttling
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Solution Overview
Problem
Modern processors face challenges in power conservation when transitioning between power states, particularly in the C1E state, where voltage compatibility is required for maximum execution and retirement rates, leading to inefficiencies in power management.
Innovation Solution
Implementing micro-architectural bandwidth throttling to reduce the voltage supply during the C1E state and upon exiting, allowing the processor to operate at a deep C1E voltage level while maintaining compatibility with the standard LFM voltage, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the processor operates in C1E state with standard LFM voltage to maintain maximum execution and retirement rates, then the processor can quickly resume full performance upon exiting C1E, but power consumption is higher than necessary
Solution Approach 1:
The processor dynamically adjusts its operational characteristics based on power state. In deep C1E state, the processor operates with throttled bandwidth limits, and upon exit, temporarily maintains throttled performance until voltage ramps to LFM level, at which point full performance is restored. This dynamic adaptation resolves the contradiction by matching performance to actual voltage conditions.
Solution Approach 2:
The invention changes the bandwidth parameter (instruction scheduling and retirement rates) to accommodate the lower voltage environment in deep C1E state. By reducing bandwidth during the voltage ramp period after C1E exit, the processor operates safely at lower voltage without requiring full LFM voltage immediately, thereby reducing power consumption while maintaining voltage compatibility.
2Use of energy by moving object
If the processor reduces voltage to deep C1E level to save power, then power consumption decreases, but the processor cannot sustain maximum instruction scheduling and retirement rates
Solution Approach 1:
The processor applies partial throttling bandwidth limits during the transition period after C1E exit, rather than immediately restoring full performance. This partial action allows the voltage to ramp to LFM level while maintaining reduced but sufficient performance, avoiding the need for full voltage immediately and thus reducing power consumption during the transition.
Solution Approach 2:
The processor preliminarily throttles bandwidth upon exiting C1E state, before voltage has fully ramped to LFM level. This preliminary action ensures voltage compatibility during the ramp period, allowing the system to benefit from lower power consumption during the transition without compromising eventual full performance.
3Productivity
If the processor maintains standard LFM voltage during C1E state, then voltage compatibility for maximum performance is ensured, but power conservation opportunities are lost
Solution Approach 1:
The processor dynamically manages the transition from deep C1E to C0 state by temporarily maintaining throttled bandwidth during the voltage ramp period. This dynamic approach allows the processor to conserve power in C1E state while ensuring smooth transition to full performance, resolving the contradiction between power conservation and performance readiness.
Data Source
AI summary
A method, device, and system are disclosed. In one embodiment the method includes supplying a processor with a first voltage. The method also includes allowing the processor to function within an enhanced processor halt state at the first voltage. The first voltage is a voltage below the lowest compatible voltage for the enhanced processor halt state. The method allows the processor to execute instructions upon waking from the enhanced processor halt state at the first voltage by throttling a maximum throughput rate of instructions being executed in the processor.