Processor Channel Multiplexing to Eliminate Duplicate Computation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing processor designs, such as those disclosed by Nield, require complex multiplexing circuitry and consume more power due to duplication of operations across parallel processing channels, which is unnecessary for gradient operations.
Innovation Solution
A circuit design that uses multiplexing circuitry to route the output of one logic unit to the output lines of both processing channels, allowing only one logic unit to perform a given operation and setting the unused unit to an idle or reduced-power state, thereby reducing the amount of multiplexing circuitry and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If duplicate computations are performed across parallel processing channels, then operational reliability is improved, but power consumption increases
Solution Approach 1:
The system dynamically switches between two operational modes: a first mode where both logic units perform duplicate computations for gradient operations, and a second mode where only one logic unit performs the computation. This dynamic adaptation allows the system to balance reliability and power consumption based on operational requirements.
Solution Approach 2:
The control circuitry changes the operational parameters of the processing channels by selectively enabling or disabling logic units based on the instruction type. For gradient operations, the system adjusts the number of active logic units from two to one, thereby changing the power consumption parameter while maintaining operational correctness through alternative routing.
2Reliability
If duplicate computations are performed across parallel processing channels, then operational reliability is improved, but device complexity increases
Solution Approach 1:
The multiplexing circuitry is designed to be dynamically reconfigurable, switching between a first configuration that supports duplicate computations and a second configuration that eliminates them. This dynamic reconfiguration reduces the effective complexity by only providing full duplicate routing when absolutely necessary, rather than permanently maintaining it.
Solution Approach 2:
The multiplexing circuitry serves multiple functions: it can route inputs to both logic units for duplicate computations, or route inputs to a single logic unit and distribute the output to multiple channels. This multi-functionality reduces the need for dedicated complex routing for each scenario, thereby reducing overall device complexity.
3Productivity
If duplicate computations are performed across parallel processing channels, then processing capability is improved, but power consumption increases
Solution Approach 1:
The system dynamically adjusts processing capability by enabling duplicate computations only when required for specific instruction types (gradient operations), and switching to single-computation mode for other operations. This dynamic adjustment maintains processing capability when needed while reducing power consumption during normal operations.
Solution Approach 2:
The control circuitry changes the operational parameters by selectively activating or deactivating logic units based on the instruction type. For gradient operations requiring duplicate computations, the system activates both logic units; for other operations, it deactivates one, thereby adjusting the processing parameter to match the actual computational requirements.
4Productivity
If duplicate computations are performed across parallel processing channels, then processing capability is improved, but device complexity increases
Solution Approach 1:
The multiplexing circuitry is designed with universal functionality that handles both duplicate computation routing and single-computation routing through the same hardware structures. This multi-functionality eliminates the need for separate dedicated routing circuits for different operational modes, thereby reducing device complexity while maintaining processing capability.
Solution Approach 2:
The system uses dynamic reconfiguration of the multiplexing circuitry to provide enhanced processing capability only when needed. The circuitry transitions between a high-capability configuration (with full duplicate routing) and a simplified configuration (with single-unit routing), thereby maintaining processing capability on demand while reducing effective device complexity.
Data Source
AI summary
A circuit for use in a processor includes a first processing channel having a first logic unit, a second processing channel having a second logic unit, and multiplexing circuitry. The multiplexing circuitry includes an input multiplexer arranged to switch between a first state in which an input of the first logic unit is coupled to an input line of the first processing channel, and a respective second state in which the input of the first logic unit is instead coupled to an input line of the second processing channel; and an output multiplexer arranged to switch between a first state in which an output line of the second processing channel is coupled to an output of the second logic unit, and a second state in which the output line of the second processing channel is instead coupled to an output of the first logic unit.