Processor Channel Multiplexing to Eliminate Duplicate Logic Operations
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Solution Overview
Problem
Existing processor designs, such as those disclosed by Nield, require complex multiplexing circuitry and consume excessive power due to duplication of operations across parallel processing channels, which is unnecessary for gradient operations.
Innovation Solution
A circuit design that uses multiplexing circuitry to route the output of one logic unit to the output lines of both processing channels, allowing only one logic unit to perform a given operation and setting the unused unit to an idle or reduced-power state, thereby reducing the need for duplicate computations and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If each processing channel has its own logic unit to perform operations independently, then processing parallelism and speed are improved, but power consumption increases due to duplicate operations
Solution Approach 1:
The patent merges the operation execution function across processing channels by allowing a single logic unit to serve multiple channels through multiplexing. Instead of each channel having its own logic unit performing duplicate operations, one logic unit is shared and controlled to perform operations for multiple channels sequentially, eliminating redundant computational work while maintaining parallel processing capability.
Solution Approach 2:
The logic unit is designed to be universal and multi-functional, capable of performing operations for multiple different processing channels. By making the logic unit universal rather than dedicated to a single channel, the system can dynamically allocate one logic unit to serve multiple channels based on operational needs, reducing the total number of logic units required and thereby reducing power consumption.
2Reliability
If each processing channel has its own logic unit for independent operation, then processing capability and reliability are improved, but device complexity increases due to additional multiplexing circuitry
Solution Approach 1:
The patent combines the operational control of multiple processing channels through a single logic unit, merging what would otherwise be separate independent operation paths. This consolidation reduces the number of separate control units and associated circuitry needed, simplifying the overall device architecture while maintaining the ability to process multiple channels reliably.
3Productivity
If duplicate logic units are used in parallel processing channels, then operational reliability and processing throughput are improved, but manufacturing cost and device area increase
Solution Approach 1:
The patent merges the functional requirements of multiple logic units into a single shared logic unit that is time-multiplexed across different processing channels. This consolidation dramatically reduces the silicon area required compared to having separate logic units for each channel, while still achieving the necessary processing throughput by efficiently allocating the shared unit across channels based on operational demand.
Data Source
Figure 1~2
Figure 3a~3b
Figure 3c
AI summary
A circuit for use in of a processor. The circuit comprises: a first processing channel comprising a first logic unit, a second processing channel comprising a second logic unit, and multiplexing circuitry. The multiplexing circuitry comprises: an input multiplexer arranged to switch between a first state in which an input of the first logic unit is coupled to an input line of the first processing channel, and a respective second state in which the input of the first logic unit is instead coupled to an input line of the second processing channel; and an output multiplexer arranged to switch between a first state in which an output line of the second processing channel is coupled to an output of the second logic unit, and a second state in which the output line of the second processing channel is instead coupled to an output of the first logic unit.