Processor Channel Multiplexing to Eliminate Duplicate Logic Operations
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Solution Overview
Problem
Existing processor designs, such as those disclosed by Nield, require unnecessary duplication of operations across parallel processing channels for gradient operations, leading to increased complexity and power consumption.
Innovation Solution
A circuit design that uses multiplexing circuitry to route the output of one logic unit to the output lines of both processing channels, allowing only one logic unit to perform an operation and setting the other to an idle or reduced-power state, thereby reducing duplication and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each processing channel has its own logic unit performing operations independently, then each channel can process its data, but power consumption increases and circuit complexity increases due to unnecessary duplication
Solution Approach 1:
The patent merges the processing functionality by allowing one logic unit to serve multiple processing channels through multiplexing. Instead of having separate logic units for each channel, the output of one logic unit is multiplexed to multiple channels, reducing the total number of logic units and their associated power consumption while maintaining processing capability across all channels.
Solution Approach 2:
The logic unit is designed to be universal and multi-functional, capable of serving multiple processing channels through the multiplexing mechanism. The same logic unit can process data for different channels at different times, making it a universal resource that reduces overall system power consumption compared to having dedicated logic units for each channel.
2Reliability
If each processing channel has its own logic unit performing operations independently, then each channel can process its data, but device complexity increases due to duplication of logic units and multiplexing circuitry
Solution Approach 1:
The patent merges the processing functionality by allowing one logic unit to serve multiple processing channels through multiplexing. Instead of having separate logic units for each channel, the output of one logic unit is multiplexed to multiple channels, reducing the total number of logic units and their associated power consumption while maintaining processing capability across all channels.
Solution Approach 2:
The patent uses a single logic unit design that can be time-shared across multiple channels, eliminating the need to physically duplicate logic units for each channel. This single design serves as a template that is reused through time-multiplexing, reducing device complexity while maintaining the ability to process data in multiple channels.
3Productivity
If logic units perform operations in parallel across all channels, then processing speed is maintained, but power consumption increases due to all units being active
Solution Approach 1:
The patent implements periodic action through time-multiplexed processing where logic units are activated in sequences rather than continuously in parallel. The processing is divided into time slots where different logic units are activated periodically to handle different channels, maintaining overall processing throughput while reducing instantaneous power consumption by keeping units idle during their non-active periods.
Solution Approach 2:
The patent introduces dynamic operation where the activation state of logic units changes over time based on processing requirements. Logic units are dynamically switched between active and idle states through the multiplexing control mechanism, allowing the system to adapt power consumption to actual processing needs while maintaining productivity through coordinated time-multiplexed operation.
Data Source
AI summary
A circuit for use in a processor includes a first processing channel having a first logic unit, a second processing channel having a second logic unit, and multiplexing circuitry. The multiplexing circuitry includes an input multiplexer arranged to switch between a first state in which an input of the first logic unit is coupled to an input line of the first processing channel, and a respective second state in which the input of the first logic unit is instead coupled to an input line of the second processing channel; and an output multiplexer arranged to switch between a first state in which an output line of the second processing channel is coupled to an output of the second logic unit, and a second state in which the output line of the second processing channel is instead coupled to an output of the first logic unit.