Processor Core Arrangement for Leakage Reduction
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Solution Overview
Problem
Modern computing systems face high power consumption due to increased leakage currents, even when devices are in idle states, which is exacerbated by the need for smaller structures and devices, and existing methods like State Retention Power Gating (SRPG) require additional area and resources.
Innovation Solution
A processor core arrangement with two or more cores, one designed for higher operation frequency with SRPG and the other without, allowing switching based on computational load to minimize average leakage by keeping the higher frequency core powered off for longer periods, thereby reducing overall power consumption without the need for SRPG features on all cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If State Retention Power Gate (SRPG) function is provided by flip-flops to store state information when powered off, then fast storage and access to state information is achieved, but additional area and resources are required
Solution Approach 1:
The patent uses a copy of the state information stored in a separate memory structure instead of using flip-flops with SRPG. The state is copied to a memory location that can retain data without power, eliminating the need for complex flip-flop-based SRPG circuitry while reducing die area.
Solution Approach 2:
The patent extracts the state retention function from the processor core itself and places it in a separate memory structure. This separation allows the core to be powered off completely without needing to maintain state information within the core's flip-flops, reducing the area required for SRPG functionality.
2Use of energy by moving object
If two processor cores are provided with different frequencies and leakages to reduce overall power consumption, then power consumption is reduced by switching between cores, but device complexity increases
Solution Approach 1:
The patent segments the processing system into two distinct cores with different frequency capabilities. One core is optimized for high-performance tasks while the other handles low-power operations, allowing the system to segment workloads appropriately and reduce overall power consumption through selective core usage.
Solution Approach 2:
The patent creates a universal processor core design that can operate in multiple frequency modes. The same core architecture can function at high frequency when needed and at low frequency for power-saving, eliminating the need for completely separate hardware designs while still achieving power reduction goals.
3Productivity
If smaller structures and devices are produced to increase processing capability, then processing power is improved, but leakage currents increase even in idle states
Solution Approach 1:
The patent changes the operational parameters of the processor cores by implementing different frequency operating modes. The low-frequency core mode reduces the switching activity and operational voltage, which directly reduces leakage currents while maintaining basic processing capability for idle or low-demand states.
Solution Approach 2:
The patent implements periodic switching between high-frequency and low-frequency core modes based on workload demands. During idle periods, the system periodically switches to the low-frequency mode to minimize leakage, then transitions back to high-frequency mode when processing demands arise, creating a periodic action pattern that balances performance and power consumption.
Data Source
AI summary
The invention relates to a method of designing a processor core arrangement which comprises a first processor core for operation at a first operation frequency and having an associated first leakage and a second processor core for operation at a second operation frequency lower than the first operation frequency and having an associated second leakage lower than the associated first leakage. The processor core arrangement is capable of switching from the first processor core to the second processor core and vice versa.