Processor Core Deactivation via Sub-Retention Voltage
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Solution Overview
Problem
Conventional techniques for deactivating processor cores in multi-core processing systems result in significant leakage current due to the application of boot voltage, leading to continued power consumption despite deactivation.
Innovation Solution
Applying a voltage less than the retention voltage, typically zero volts, to the processor core, and using a voltage controller to tie voltage inputs together, along with clock gating or reducing clock frequency, to effectively deactivate the core.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If boot voltage is applied to deactivate a processor core, then basic operations can still be performed, but significant leakage current occurs causing continued power consumption
Solution Approach 1:
The patent changes the voltage parameter from boot voltage to a voltage below retention voltage, fundamentally altering the electrical state of the processor core to achieve complete deactivation while preserving silicon state. This parameter change eliminates leakage current and stops power consumption.
Solution Approach 2:
Instead of applying a reduced voltage (boot voltage) to deactivate the core, the patent applies the opposite approach by using a voltage significantly below retention voltage, effectively inverting the conventional deactivation method to achieve complete power shutdown.
2Adaptability or versatility
If boot voltage is applied to deactivated processor core, then basic operations and instruction execution are permitted, but leakage current increases significantly
Solution Approach 1:
The patent fundamentally changes the voltage parameter from boot voltage to below-retention voltage, which eliminates the harmful leakage current while maintaining the ability to preserve silicon state for future activation.
Solution Approach 2:
The patent converts the potentially harmful effect of voltage application into a beneficial outcome by using a voltage below retention voltage, which not only eliminates leakage current but also preserves the silicon state for future use, turning what could be harmful into a beneficial deactivation method.
3Productivity
If normal operating voltage is applied to deactivated processor core, then full functionality is maintained, but power consumption increases
Solution Approach 1:
The patent applies a voltage parameter change from normal operating voltage to below-retention voltage, which reduces power consumption to minimal levels while preserving the silicon state, allowing the core to be deactivated without sacrificing future activation capability.
Data Source
AI summary
A method includes applying a voltage to a first processor core of a plurality of processor cores to deactivate the first processor core, the voltage less than a retention voltage of the first processor core. The application of the voltage can be in response to a software setting. The software setting can be configured via a user input, a software application, an operating system, or a BIOS setting. Alternately, the application of the voltage can be in response to a permanent hardware setting, such as the state of a fuse associated with the first processor core.


