Processor Register Sampling for Crash-State Instruction Capture

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Solution Overview

Problem

Existing processor architectures lack effective methods for analyzing the last instructions and interrupts executed before a crash, and they do not facilitate non-intrusive statistical profiling of processor core execution.

Innovation Solution

Implementing a system that samples and stores program and exception program counters in capture registers during processor resets, allowing for the preservation and analysis of these values to identify the last instructions and interrupts before a crash, and enabling non-intrusive statistical profiling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional processor architectures are used without register sampling, then the processor operates with standard functionality, but the ability to analyze crashed state and perform statistical profiling is lost

Engineering Contradiction:
Improvecrash analysis capabilityVSAvoidprocessor architecture complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by sampling and storing register values (program counter, exception program counter) into capture registers before a crash occurs. The sampling circuit continuously captures register states and holds them in capture registers until a crash is detected, ensuring the crashed state information is preserved without requiring complex post-crash analysis mechanisms.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary sampling circuit that acts as a mediator between the processor core registers and the external analysis system. This sampling circuit includes capture registers that hold register values and control logic that manages the sampling process, providing a buffer layer that simplifies both the processor core and the external debugging infrastructure.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Difficulty of detecting and measuring

If register sampling and capture functionality is added to enable crash analysis, then diagnostic capabilities are improved, but the processor architecture becomes more complex

Engineering Contradiction:
Improvecrashed state detectionVSAvoidprocessor architecture
Core Design Contradiction:
Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The patent extracts the crash analysis functionality from the main processor core by implementing a separate sampling circuit with capture registers. This dedicated sampling infrastructure is taken out as an independent module that parallels the processor core, allowing crash state capture without modifying the core instruction execution path or requiring complex integration with the processor's control logic.

Inventive Principle:
Principle #2Taking out (Extraction)

3Measurement precision

If continuous register sampling is performed, then statistical profiling accuracy is improved, but the processing overhead and resource consumption increase

Engineering Contradiction:
Improvestatistical profiling precisionVSAvoidinstruction execution throughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The sampling circuit operates autonomously using processor-generated signals (iretire for instruction retirement, reset for core reset) to trigger sampling operations. The circuit self-manages the capture process without requiring external control logic or interrupting the processor's instruction execution flow, thereby maintaining high measurement precision while minimizing overhead.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12625756B2Processor crash analysis using register sampling
Publication Date: 2026.05.12 SIFIVE INC
  • US12625756B2 patent drawing
  • US12625756B2 patent drawing
  • US12625756B2 patent drawing

AI summary

Systems and methods are disclosed for processor crash analysis using register sampling. For example, an integrated circuit may include a processor core configured to execute instructions, wherein the processor core includes a program counter register and an exception program counter register (e.g., a machine exception program counter register) that is configured to store a program counter value that was current when an exception occurred; a data store connected to the exception program counter register via an ingress port that is configured to store a copy of an exception program counter value responsive to retirement of an instruction; and an exception program counter capture register, configured to store an exception program counter value from the second data store responsive to a reset signal for the processor core.