Processor Successive Dependent Instruction Execution
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Solution Overview
Problem
Current processor designs face inefficiencies due to a single output bus causing wire congestion, which necessitates the allocation of two output results of a fused instruction across consecutive cycles, hindering the execution of successive dependent instructions.
Innovation Solution
A method is introduced to execute successive dependent instructions by loading operands in a single instruction cycle, allowing the first instruction to be executed in one processor cycle, with its result used in the next cycle for the second instruction, and the second instruction's result available in a subsequent cycle, thereby reducing read accesses and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single output bus is used in the processor, then wire congestion is reduced and device complexity is minimized, but the execution speed of successive dependent instructions deteriorates because results must be allocated across consecutive cycles
Solution Approach 1:
The patent applies preliminary action by loading operands for both the first and second instructions simultaneously in advance, before the first instruction executes. This allows the second instruction to be ready to execute immediately after the first instruction completes, eliminating waiting time and enabling continuous operation without requiring additional output bus bandwidth.
2Ease of operation
If operands for multiple instructions are loaded in separate cycles, then the single output bus can handle data flow, but the time to supply results increases and calculation speed deteriorates
Solution Approach 1:
The patent merges the operand loading operations for the first and second instructions into a single simultaneous loading operation. Both instructions receive their required operands during the same cycle, consolidating what would traditionally be separate loading phases into one unified operation, thereby reducing the total time required to prepare and execute both instructions.
Data Source
AI summary
The present disclosure relates to a method to execute successive dependent instructions from an instruction stream in a processor. In an embodiment, the invention relates to a method to execute successive dependent instructions from an instruction stream in a processor. The method may include identifying a first instruction and a second instruction. A given operand of a second instruction is an output of the first instruction of the pair. The first instruction is older than the second instruction. The method may include loading the operands of the first instruction and the second instruction. The method may include executing the first instruction and the second instruction.