Tap-Sampled Delay Line for Processor Voltage Droop Detection
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Solution Overview
Problem
Voltage droop in processor supply voltage can lead to timing failures due to sudden changes in effective switched capacitance and clock frequency, which existing technologies struggle to rapidly and accurately detect and mitigate.
Innovation Solution
A method and apparatus using a tap sampled delay line to detect voltage droop by measuring changes in clock edge position, and reactively generating a lower-frequency processor clock signal by removing a proportion of clock pulses to mitigate the droop, ensuring stable processor operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor clock frequency is suddenly increased to execute applications faster, then productivity is improved, but voltage droop occurs causing timing failures
Solution Approach 1:
The voltage droop detection mechanism is activated before the frequency switch occurs. The system continuously monitors voltage droop conditions and prepares to detect the droop event as it happens, enabling early intervention before timing failures occur.
Solution Approach 2:
The system uses feedback from voltage droop detection to control the frequency switching operation. When voltage droop is detected during or after a frequency increase, the system can adjust subsequent frequency switching behavior to prevent timing failures while still maintaining high productivity.
2Productivity
If the effective switched capacitance is suddenly increased to improve computational intensity, then productivity is improved, but voltage droop occurs causing timing failures
Solution Approach 1:
The detection mechanism is prepared in advance to monitor voltage droop conditions that may result from sudden increases in effective switched capacitance. This allows the system to detect and respond to droop events before they cause timing failures.
Solution Approach 2:
The system incorporates feedback from voltage droop detection to control future computational intensity adjustments. When droop is detected following an increase in switched capacitance, the system can modulate subsequent computational workload to prevent timing failures while maintaining overall productivity.
3Measurement precision
If conventional voltage droop detection methods are used, then device complexity is reduced, but detection precision and speed are insufficient to prevent timing failures
Solution Approach 1:
The patent introduces an intermediary detection mechanism that indirectly measures voltage droop effects through their impact on clock signal timing. This approach achieves high measurement precision without requiring direct complex voltage measurement circuitry, as the timing shifts serve as a sensitive indicator of voltage droop conditions.
Data Source
AI summary
During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly and accurately detecting this droop so as to reduce the probability of circuit timing failures. The droop detector described herein uses a tap sampled delay line in which a clock signal is split along two separate paths. Each of the taps in the paths are separated by two inverter delays such that the set of samples produced represent sample values of the clock signal that are each separated by a single inverter delay without inversion of the first clock signal between the samples.