Multi-Core Processor Power Management via Dynamic Current Limiting
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Solution Overview
Problem
Existing multi-core processor systems face limitations in high-frequency operation due to asynchronous wakeup events from idle cores, which can overload the power supply and cause system failure, and existing solutions require modifications to the power-management unit, making them incompatible with unmodified chips.
Innovation Solution
A system that detects changes in active and constrained processor cores, computes a new current limit (ICCMAX) to account for power saved by constrained cores, and communicates this to the power-management mechanism, allowing for reduced frequency operation of idle cores to allocate more power to active cores, thereby enabling high-frequency operation without overloading the power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If processor cores are placed in idle state with asynchronous wakeup events, then power consumption is reduced, but system reliability deteriorates due to potential power overload when cores resume operation
Solution Approach 1:
The patent applies preliminary action by detecting wakeup events before the idle core actually resumes operation. The system proactively identifies when an idle core has pending wakeup events and pre-calculates the power implications, allowing the power management unit to adjust frequency allocations in advance. This prevents the power overload condition from occurring when the core resumes, thereby maintaining system reliability while still enabling power-saving idle states.
2Reliability
If overclocking of non-idle cores is avoided when idle cores have wakeup events, then system reliability is maintained, but productivity deteriorates due to reduced operating frequency
Solution Approach 1:
The patent implements dynamics by making the frequency allocation adaptive and dynamic rather than static. The power management unit continuously monitors the state of processor cores and dynamically adjusts frequency allocations based on real-time conditions. When idle cores are truly idle without upcoming wakeup events, non-idle cores can operate at higher frequencies. When wakeup events are detected, the system dynamically recalculates power availability and adjusts frequencies accordingly. This dynamic approach allows the system to maximize productivity when safe to do so while maintaining reliability when necessary.
3Productivity
If modified power-management unit is used to facilitate high-frequency operation, then productivity improves, but ease of manufacture deteriorates due to requirement for modified processor chips
Solution Approach 1:
The patent applies universality by designing a power management approach that works with existing, unmodified processor chips. Rather than requiring specialized hardware modifications, the invention uses the existing power management unit in standard processors and extends its functionality through software-based event detection and power calculation mechanisms. The system leverages existing processor features and interfaces, making the solution universally applicable to current processor architectures without requiring custom hardware modifications, thereby maintaining ease of manufacture while achieving improved productivity.
Data Source
AI summary
The disclosed embodiments provide a system that facilitates power management in a multi-core processor. During operation, the system detects a change related to a number of active processor cores in the multi-core processor. (Within this system, a given processor core can reside in an active state, wherein the given processor core can draw an active power, or alternatively in a constrained state, wherein the given processor core can draw a constrained power, which is less than the active power.) In response to detecting the change, the system computes a new current limit ICCMAX for the multi-core processor based on the number of active and constrained processor cores. Finally, the system communicates ICCMAX to a power-management mechanism within the multi-core processor. This enables the power-management mechanism to use ICCMAX to account for power saved by the constrained processor cores when the multi-core system is subsequently determining whether to change its operating frequency.