Processor Execution Point Alignment via Instruction Data Exchange
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Solution Overview
Problem
Loosely lock-stepped processors face challenges in determining the execution point of duplicate user program copies due to slight differences in clocking frequency and inaccuracies in retired instruction counters, making it difficult to identify which processor leads or lags, especially in fault detection and correction scenarios.
Innovation Solution
The implementation of synchronization logic across processors to coordinate interrupts and align execution points by exchanging information through synchronization registers and voter logic, ensuring that all processors service interrupts at the same point in the instruction stream, and using uncooperative process handlers to identify and align lagging processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If processors execute duplicate user programs independently with different clocking frequencies, then productivity is improved, but the ability to determine execution point alignment deteriorates
Solution Approach 1:
The patent introduces an intermediary mechanism (the system that exchanges information about executed instructions) that mediates between the independent processor executions and the need for synchronization. This intermediary enables alignment of execution points without requiring the processors to execute at the same speed or in a coordinated manner, thus resolving the contradiction between productivity and measurement precision.
2Ease of operation
If retired instruction counters are used to track execution progress, then ease of operation is improved, but measurement precision deteriorates due to counting inaccuracies
Solution Approach 1:
The patent implements a feedback mechanism where processors exchange information about the instructions they have executed. This feedback loop allows the system to detect and correct discrepancies in execution point determination that arise from inaccurate retired instruction counters, thereby maintaining both ease of operation and measurement precision.
Solution Approach 2:
The patent replaces the mechanical/intrinsic counter-based tracking system with an information-exchange-based system. Instead of relying solely on processor-internal counters that may be inaccurate, the system uses inter-processor communication to determine execution points, substituting a less precise but more reliable method.
3Productivity
If processors operate independently without synchronization, then productivity is improved, but reliability deteriorates due to inability to detect computational faults
Solution Approach 1:
The patent uses an intermediary information exchange mechanism that allows independent processors to maintain reliability. The system enables fault detection by comparing executed instructions between processors without requiring them to execute in a coordinated manner, thus preserving both productivity and reliability.
Solution Approach 2:
The patent employs duplicate copies of user programs executing on different processors. By maintaining these copies and exchanging information about their execution, the system can detect computational faults through comparison while allowing each processor to execute independently for maximum productivity.
Data Source
AI summary
A method and system of aligning execution point of duplicate copies of a user program by exchanging information about instructions executed. At least some of the exemplary embodiments may be a method comprising operating duplicate copies of a user program in a first and second processor, allowing at least one of the user programs to execute until retired instruction counter values in each processor are substantially the same, and then executing a number of instructions of each user program. Of the instructions executed, at least some of the instructions are decoded and the inputs of each decoded instruction determined (the decoding substantially simultaneously with executing in each processor). The method further comprises exchanging among the processors addresses of decoded instructions and values indicative of inputs of the decoded instructions, determining that an execution point of the user program in the first processor lags with respect to an execution point of the user program in the second processor using at least the addresses of the decoded instructions, and advancing the first processor until the execution point within each user program is substantially aligned.


