Privilege Level Aware Processor Hardware Resource Management

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Solution Overview

Problem

Existing systems lack discrete management of hardware facilities among applications, supervisors, and hypervisors, leading to inefficiencies in context swap overhead and security concerns due to lack of precise tracking and allocation of resource usage across privilege levels.

Innovation Solution

A processor core with hardware facility usage status and control registers allows the hypervisor and supervisor to determine usage by lower privilege levels, enabling more precise management of resource allocation and security through separate flags for each privilege level, reducing context swap overhead and preventing covert channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the hypervisor saves and restores facility state for every partition context swap, then security is maintained by preventing covert channels, but context swap overhead increases

Engineering Contradiction:
ImprovesecurityVSAvoidcontext swap overhead
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent changes the parameter of facility state management by introducing usage status flags that indicate whether a facility has been modified. Instead of blindly saving and restoring all facility states, the system checks these flags to determine which facilities actually require state preservation, thereby reducing unnecessary save/restore operations while maintaining security.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The facility usage status flags automatically track whether facilities have been used or modified by the partition. This self-tracking mechanism eliminates the need for the hypervisor to manually monitor and determine which facilities require state saving, enabling efficient automated decision-making about context swap operations.

Inventive Principle:
Principle #25Self-service

2Productivity

If the supervisor tracks all facility usage, then facility allocation management is improved, but system complexity increases

Engineering Contradiction:
Improvefacility allocation managementVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments facility tracking into two distinct layers: the supervisor layer that manages application-level facility usage, and the hypervisor layer that manages partition-level facility usage. Each layer has its own set of usage status flags. This segmentation allows the supervisor to focus only on application-related facility tracking without bearing the burden of entire system-wide facility management, thereby reducing supervisor complexity while improving facility allocation management.

Inventive Principle:
Principle #1Segmentation

3Ease of operation

If all facilities are initially enabled, then ease of operation is improved, but security risk increases due to potential covert channels

Engineering Contradiction:
Improvefacility accessVSAvoidcovert channel risk
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by pre-setting all facility usage status flags to indicate 'not used' state before partition execution begins. This preliminary configuration establishes a secure baseline that prevents covert channels, while still allowing facilities to be accessed when needed. The flags are prepared in advance to track actual usage, combining security with operational flexibility.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8695010B2Privilege level aware processor hardware resource management facility
Publication Date: 2014.04.08 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US8695010B2 patent drawing
  • US8695010B2 patent drawing
  • US8695010B2 patent drawing

AI summary

Multiple machine state registers are included in a processor core to permit distinction between use of hardware facilities by applications, supervisory threads and the hypervisor. All facilities are initially disabled by the hypervisor when a partition is initialized. When any access is made to a disabled facility, the hypervisor receives an indication of which facility was accessed and sets a corresponding hardware flag in the hypervisor's machine state register. When an application attempts to access a disabled facility, the supervisor managing the operating system image receives an indication of which facility was accessed and sets a corresponding hardware flag in the supervisor's machine state register. The multiple register implementation permits the supervisor to determine whether particular hardware facilities need to have their state saved when an application context swap occurs and the hypervisor can determine which hardware facilities need to have their state saved when a partition swap occurs.