Processor Instruction Memory Data Pointer Register Architecture
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Solution Overview
Problem
Conventional processor architectures face inefficiencies when handling large constants, as they often require instruction fragmentation, increased execution time, and latency issues due to memory access permissions and caching problems.
Innovation Solution
The proposed processor architecture incorporates a data pointer register and data buffer to handle large constants efficiently, allowing for direct access to data values within the instruction memory, reducing the need for additional instructions and minimizing latency by preloading data values into the cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional processor architectures are used to handle large constants, then the constants can be stored in memory, but the execution time increases due to instruction fragmentation and additional memory access operations
Solution Approach 1:
The patent embeds constant values directly within the instruction stream by nesting them in the upper bits of instruction words. This allows constants to be fetched along with instructions in the same memory access cycle, eliminating separate memory access operations and reducing execution time while maintaining the ability to handle large constant values
2Quantity of substance
If instruction fragmentation is used to handle large constants, then the constants can be stored in smaller segments, but the device complexity increases due to additional instructions and memory access operations
Solution Approach 1:
The patent merges the constant value storage with the instruction storage by utilizing unused bits in the instruction format. This combining approach allows constants to be embedded within instructions, eliminating the need for separate instruction sequences to load constants into registers, thereby reducing device complexity while maintaining support for large constant values
3Ease of operation
If data values are placed in instruction memory, then direct access is possible, but read permissions are required which may compromise security
Solution Approach 1:
The patent applies local quality by using only specific unused bits within instruction words to store constant values, rather than requiring separate data storage regions with read permissions. This localized use of instruction bits allows direct access during instruction fetch without compromising security, as no additional read permission requirements are introduced
4Adaptability or versatility
If constants are stored in separate memory locations, then they can be accessed independently, but access latency increases due to cache misses and memory access permissions
Solution Approach 1:
The patent employs preliminary action by pre-positioning constant values within the instruction stream during instruction encoding. This allows constants to be fetched simultaneously with instructions during the normal instruction fetch phase, eliminating subsequent memory access operations and reducing access latency while maintaining flexibility in constant value usage
Data Source
AI summary
Disclosed is a digital processor comprising an instruction memory having a first input, a second input, a first output, and a second output. A program counter register is in communication with the first input of the instruction memory. The program counter register is configured to store an address of an instruction to be fetched. A data pointer register is in communication with the second input of the instruction memory. The data pointer register is configured to store an address of a data value in the instruction memory. An instruction buffer is in communication with the first output of the instruction memory. The instruction buffer is arranged to receive an instruction according to a value at the program counter register. A data buffer is in communication with the second output of the instruction memory. The data buffer is arranged to receive a data value according to a value at the data pointer register.