Processor Jump Inhibitor Hides Forward Jumps from Side-Channel Leakage
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Solution Overview
Problem
Computer processors, particularly in smart cards, leak secret information through side-channels such as power consumption and electromagnetic radiation, especially due to conditional jumps, which can be exploited by attackers to derive secret conditions.
Innovation Solution
A computer processor with a jump handler that detects forward jumps and inhibits their execution, executing intermediate instructions between the jump and its target, and modifying storage destinations to suppress the effects of these jumps, thereby reducing information leakage through side-channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conditional jump instructions are executed to control program flow based on secret information, then program execution logic is improved, but side-channel information leakage increases
Solution Approach 1:
The patent introduces an intermediary mechanism between the jump instruction and the actual program flow control. A dummy instruction is inserted as a mediator that executes regardless of the jump condition, preventing the direct correlation between secret information and observable execution behavior. This intermediary dummy instruction acts as a buffer that masks the true program flow decisions from side-channel observers.
Solution Approach 2:
The patent creates a copy of the program execution path by introducing dummy instructions that replicate the appearance of actual execution paths. The dummy instructions generate identical side-channel signals (power consumption, timing) as real instructions would, making it impossible for attackers to distinguish between executed and skipped paths based on side-channel measurements alone.
2Reliability
If forward jumps are inhibited to reduce information leakage, then security against side-channel attacks is improved, but execution time increases
Solution Approach 1:
The patent applies partial inhibition by only targeting forward jumps (which are more susceptible to information leakage) while allowing backward jumps to execute normally. This selective approach provides security benefits without the full performance penalty of inhibiting all jump instructions. The dummy instruction is inserted only when necessary, minimizing the overhead to execution time.
Solution Approach 2:
The dummy instruction is designed as a lightweight, temporary construct that performs its security function and then disappears. It executes a simple operation (such as reading from a fixed memory location or performing a no-op) and is discarded after use. This cheap dummy instruction provides strong security masking with minimal computational cost compared to the full program execution.
3Loss of information
If dummy instructions are inserted to mask jump effects, then correlation between side-channels and secret information is reduced, but processor complexity increases
Solution Approach 1:
The dummy instruction mechanism is implemented using existing processor resources and instruction execution capabilities. The same execution unit, memory access mechanisms, and pipeline infrastructure that handle normal instructions are used to execute dummy instructions. This self-service approach leverages the processor's existing architecture rather than requiring separate dedicated hardware for security functions.
Solution Approach 2:
The patent changes the parameter of instruction execution by modifying the target address of jump instructions dynamically. Instead of changing the fundamental architecture or adding complex hardware, the system changes the behavioral parameter of instruction execution by inserting dummy instructions at specific locations, thereby altering the observable execution trace without structural complexity changes.
Data Source
AI summary
A computer processor is provided which hides jump instructions, in particular condition jump instructions, from side-channels. The processor comprises a forward jump detector for detecting a forward jump instruction having a jump target location which lies ahead and a jump inhibitor for inhibiting an execution of the forward jump instruction. The computer processor is configured for executing at least one intermediate computer instruction located between the inhibited forward jump instruction and the jump target location. The processor further comprises a storage destination modifier for modifying the storage destination determined by the at least one intermediate computer instruction to suppress the effects of execution of intermediate instructions. Since the intermediate instruction is executed regardless of the forward jump instruction, the jump is hidden in a side-channel. Secret information, such as cryptographic keys, on which the forward jump may depend, is also hidden.