Processor Memory Co-Exploration Across Abstraction Levels
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Solution Overview
Problem
Current design methodologies for application-specific instruction set processors (ASIP) lack efficient tools for processor/memory co-exploration at multiple abstraction levels, particularly in heterogeneous memory architectures, limiting the ability to merge processor core and memory subsystem design effectively.
Innovation Solution
A unified approach using an architecture description language (ADL) for processor/memory co-exploration, enabling modeling at both functional and cycle-accurate levels, with a communication protocol formed from primitives for simulation, and application program interfaces (APIs) to generate simulation models suitable for various abstraction levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If cycle-accurate memory modeling is used in processor/memory co-exploration, then simulation accuracy is improved, but simulation performance and exploration efficiency deteriorate
Solution Approach 1:
The patent segments the design exploration process into multiple abstraction levels: functional level for early exploration and cycle-accurate level for detailed verification. This segmentation allows designers to perform rapid functional simulations first, then proceed to more accurate but slower cycle-accurate simulations only when necessary, thereby resolving the contradiction between accuracy and efficiency.
Solution Approach 2:
The patent introduces dynamic switching between different abstraction levels based on exploration needs. The simulation model can dynamically transition from functional level to cycle-accurate level and vice versa, allowing the system to adapt the level of detail to the current exploration phase, thus balancing accuracy requirements with exploration efficiency.
2Manufacturing precision
If processor core and memory subsystem design are merged into unified design process, then design quality is improved, but design complexity increases
Solution Approach 1:
The patent creates a universal design framework that can handle both processor core design and memory subsystem design within a single unified environment. The framework provides multi-functional capabilities including functional simulation, cycle-accurate simulation, and co-exploration tools that work across different design domains, reducing the need for separate design processes while managing complexity through standardization.
Solution Approach 2:
The patent introduces an intermediary unified design framework that mediates between processor core design and memory subsystem design. This framework provides standardized interfaces and common exploration tools that facilitate integration while abstracting away the underlying complexity, allowing designers to work with a unified model without being overwhelmed by the full complexity of both subsystems simultaneously.
3Adaptability or versatility
If multiple abstraction levels are supported for processor/memory modeling, then design flexibility is improved, but tool complexity increases
Solution Approach 1:
The patent implements a nested structure where functional-level models contain simplified representations that can be progressively refined into cycle-accurate models. Each abstraction level is nested within the next, with the functional level providing the outer container and cycle-accurate details nested inside when needed. This nested organization allows flexible switching between levels while managing tool complexity through hierarchical structuring.
Data Source
AI summary
Processor/memory co-exploration at multiple abstraction levels. An architecture description language (ADL) description of a processor/memory system is accessed. The ADL description models on one of a plurality of abstraction levels. The abstraction levels may include a functional (or bit-accurate) level and a cycle-accurate level. Further, a communication protocol for the processor/memory system is accessed. The communication protocol is formed from primitives, wherein a memory interface formed from the primitives is useable in simulation at the abstraction levels. A processor/memory simulation model is automatically generated from the description and description of the communication protocol. The processor/memory simulation model comprises a processor/memory interface comprising the primitives and based on the communication protocol. The memory interface allows simulation of the processor/memory on the appropriate abstraction level for the simulation. For example, the processor/memory interface may be a functional interface or a cycle-accurate interface.