Semiconductor Package Layout With Processor-on-Memory Load Sharing
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Solution Overview
Problem
Next-generation memory semiconductors face challenges in processing large amounts of data quickly, leading to increased load on memory semiconductor devices, which can be alleviated by integrating a processor chip with a memory chip in a semiconductor package to distribute processing tasks and reduce electrical load.
Innovation Solution
A semiconductor package design that includes a memory chip with a redistribution layer connected to chip pads, a processor chip mounted on the redistribution layer, and conductive structures extending through a sealing member to increase robustness and reliability, allowing for efficient data processing and reducing the load on the memory chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a processor chip is integrated with a memory chip in a semiconductor package, then the electrical load on the memory chip is reduced and space utilization is enhanced, but the device complexity increases
Solution Approach 1:
The patent combines the memory chip and processor chip into a single semiconductor package, allowing them to share common structures such as the redistribution layer and sealing member. This merging approach reduces the overall electrical load on the memory chip while enhancing space utilization, and the shared structures help manage the complexity by consolidating common functions.
Solution Approach 2:
The redistribution layer acts as an intermediary between the memory chip and processor chip, providing electrical connections and signal routing. This mediator structure enables efficient communication between the two chips while managing the complexity of inter-chip connections through a standardized interface layer.
2Reliability
If the diameter and thickness of conductive structures are increased to increase robustness and reliability, then adhesion issues and copper depletion are addressed, but the manufacturing precision requirements increase
Solution Approach 1:
The patent modifies the physical parameters of the conductive structures by increasing their diameter and thickness. This parameter change directly addresses adhesion issues and copper depletion problems, making the conductive structures more robust. The standardized dimensions also simplify manufacturing by providing clear design specifications.
Solution Approach 2:
The conductive structures utilize composite material layers including copper, nickel, and solder materials. This composite approach enhances adhesion between different layers and provides corrosion resistance, while the multi-layer structure allows for optimized electrical and mechanical properties without requiring excessive precision in any single layer.
Data Source
AI summary
A semiconductor package includes a memory chip having chip pads on a first surface thereof. A redistribution layer is formed on the first surface of the memory chip. The redistribution layer is electrically connected to the chip pads. The redistribution layer has first redistribution pads on a first surface of the redistribution layer in a first region and a plurality of second redistribution pads on the first surface of the redistribution layer in a second region thereof. A processor chip is disposed on the first region of the redistribution layer and is electrically connected to the first redistribution pads. A sealing member is disposed on the first surface of the redistribution layer and covers the processor chip. Conductive structures are on the second region and penetrate through the sealing member and extend upwardly in a vertical direction away from the second redistribution pads.