Unified Processor-Memory Stack With Vertical Bonding for RC Delay
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Solution Overview
Problem
Conventional semiconductor devices face issues with cross-talk and high loading on processors due to long-distance metal connections between different memory types, leading to RC delays and increased chip area, especially in systems requiring heterogeneous memory architectures.
Innovation Solution
A unified semiconductor device integrates a processor core, cache, and heterogeneous memories (DRAM and NAND) in a multi-chip package with short-distance vertical metal interconnects, eliminating bus interface units and reducing chip size through direct bonding of memory cells and processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If separate logic die and memory die are used, then manufacturing complexity is reduced, but inter-die coupling and signal integrity issues arise
Solution Approach 1:
The patent combines the logic die and memory die into a single unified semiconductor device structure. The logic circuit and memory circuit are formed on the same semiconductor substrate with direct interconnection, eliminating the need for separate dies and inter-die coupling. This merging approach maintains signal integrity while integrating multiple functions in one device.
2Reliability
If memory devices are integrated onto the logic die, then inter-die coupling is eliminated, but logic die manufacturing becomes more complex
Solution Approach 1:
The patent segments the unified semiconductor device into distinct logic circuit regions and memory circuit regions on the same substrate. Each region can be independently designed and optimized while maintaining direct integration. This segmentation allows standardized memory array designs to be combined with logic circuits without significantly complicating the overall manufacturing process.
3Ease of manufacture
If memory circuit is formed prior to logic circuit, then memory array formation is simplified, but via formation through memory array becomes difficult
Solution Approach 1:
The patent forms preliminary via structures through the memory array region before completing the memory cell formation. These preliminary vias are then reused and extended in subsequent processing steps to become the final interconnect vias. This preliminary action simplifies the overall via formation process by eliminating the need to create new vias through the completed memory array later.
4Ease of manufacture
If logic circuit is formed prior to memory circuit, then logic device integration is simplified, but memory array via formation becomes difficult
Solution Approach 1:
The patent structures the memory array and logic circuit regions in a nested or interleaved manner on the semiconductor substrate. The memory array regions are positioned such that logic circuit regions can be formed around or between them, allowing both circuits to be integrated without requiring complex via formation through dense memory structures. This spatial nesting facilitates easier manufacturing.
Data Source
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Figure 3A~3B
Figure 4A~4B
AI summary
A semiconductor device includes a first semiconductor structure (702) including NAND memory cells and a first bonding layer (730) including first bonding contacts (732), a second semiconductor structure (704) including DRAM cells and a second bonding layer (750) including second bonding contacts (752), a third semiconductor structure (706) including a processor (716), SRAM cells (718), and a third bonding layer (726) including third bonding contacts (728). The semiconductor device further includes a first bonding interface (708) between the first and third bonding layers, and a second bonding interface (710) between the second and third bonding layers. The first bonding contacts (732) are in contact with a first set of the third bonding contacts (728) at the first bonding interface (708). The second bonding contacts (752) are in contact with a second set of the third bonding contacts (728) at the second bonding interface (710). The first and second bonding interfaces are in a same plane.