Pipelined Processor Multi-Issue Microcode Branch Decoder
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Solution Overview
Problem
Conventional processors are limited by fetching a single microcode instruction per clock cycle, which restricts the performance of micro-coded architectural instructions and exception service routines, especially in superscalar processors that can execute multiple instructions per clock.
Innovation Solution
The processor design includes an instruction translator that fetches multiple microcode instructions per clock cycle, translating architectural instructions into microinstructions, and utilizes a microcode unit to execute these instructions out of program order, enhancing the execution pipeline's throughput and exception handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single microcode instruction is fetched per clock cycle, then the processor maintains simple control logic and stable operation, but the performance of micro-coded architectural instructions and exception service routines is limited
Solution Approach 1:
The microcode unit is divided into multiple functional segments including a microcode ROM for storing instructions, a branch decoder for detecting branch instructions, and a queue for buffering fetched microcode instructions. This segmentation allows parallel processing of multiple microcode instructions while maintaining organized control logic for each functional block.
Solution Approach 2:
The system dynamically adapts its behavior based on the presence of branch instructions. When no branch instructions are detected in the fetched microcode instructions, the system operates in high-throughput mode fetching multiple instructions per clock cycle. When branch instructions are present, the system switches to sequential processing mode, dynamically adjusting the fetch rate to maintain correctness while optimizing performance.
2Productivity
If multiple microcode instructions are fetched per clock cycle, then the throughput of microinstructions is increased, but the complexity of the fetching and decoding mechanism increases
Solution Approach 1:
The system performs preliminary detection of branch instructions in the fetched microcode instructions before full processing. The branch decoder examines the fetched instructions in advance to determine if any contain branch operations, allowing the system to prepare appropriate processing modes before execution begins, thus managing complexity through advance preparation.
Solution Approach 2:
A queue structure serves as an intermediary between the microcode ROM and the execution units. This queue buffers multiple fetched microcode instructions and manages their flow to the execution pipeline, decoupling the high-throughput fetching mechanism from the execution stage and simplifying the overall control logic by introducing this intermediate buffering layer.
3Productivity
If branch instructions are resolved by the execution pipeline, then the processor maintains a unified resolution mechanism, but micro-coded instructions and exception routines experience performance bottlenecks
Solution Approach 1:
The branch decoding and resolution functionality is extracted from the general execution pipeline and placed directly within the microcode unit. This allows branch instructions in microcode to be resolved locally and efficiently without burdening the main execution pipeline, while non-branch microcode instructions continue to flow through the pipeline normally. This extraction creates a specialized fast path for branch resolution in microcode contexts.
Solution Approach 2:
The microcode unit performs self-service by independently detecting and resolving its own branch instructions through the integrated branch decoder. This self-contained approach allows the microcode unit to manage its own control flow without external intervention from the execution pipeline, improving performance for micro-coded exception handling while maintaining a relatively simple overall architecture.
Data Source
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AI summary
A processor has an execution pipeline that executes microinstructions and an instruction translator that translates architectural instructions into the microinstructions. The instruction translator has a memory that holds microcode instructions and provides a fetch quantum of a plurality of microcode instructions per clock cycle, a queue that holds microcode instructions provided by the memory, and a branch decoder that decodes the fetch quantum to detect local branch instructions, causes microcode instructions of the fetch quantum up to but not including a first-in-program-order local branch instruction to be written to the queue, and prevents the first-in-program-order local branch instruction and following microcode instructions of the fetch quantum from being written to the queue. Local branch instructions are resolved by the instruction translator rather than the execution pipeline. Microcode translators translate multiple microcode instructions received from the queue per clock cycle into microinstructions for provision to the execution pipeline.