Processor Core Multiplier Supporting Vector and Single Value Multiplication
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Solution Overview
Problem
Modern applications require processors that can seamlessly integrate both general-purpose processing and digital signal processing capabilities, which existing processors fail to achieve effectively, leading to a need for a solution that supports vector and single value multiplication, fractional arithmetic, saturation, and SIMD operations.
Innovation Solution
The processor core design includes a multiplier that generates partial products for vector and single values, utilizing Booth recoding to reduce the number of partial products, and combines them using adder arrays and a combiner to support various operations such as vector multiply, dot-product accumulate, and multiply-difference accumulate, while handling fractional values and saturation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a processor is designed to support both GPP and DSP functionality, then processing versatility is improved, but device complexity increases
Solution Approach 1:
The multiplier is designed to perform multiple functions: it can execute both vector multiplication (DSP operation) and single-value multiplication (GPP operation) using the same hardware circuit. The combiner unit dynamically selects and combines partial products from different adder arrays to produce different operation results, enabling one hardware structure to serve multiple processing purposes without requiring separate dedicated circuits for each operation type.
2Adaptability or versatility
If the multiplier supports vector multiplication, then DSP capability is improved, but the ability to handle single value operations efficiently deteriorates
Solution Approach 1:
The multiplier is segmented into independent functional components: multiple adder arrays that can be selectively activated, and a combiner unit that selectively combines partial products. When performing single-value multiplication, only the necessary adder arrays are activated while others remain idle, allowing the hardware to efficiently handle scalar operations without being constrained by vector processing requirements. This segmentation enables dynamic resource allocation based on operation type.
3Ease of manufacture
If the processor structure is simplified to reduce complexity, then ease of manufacture is improved, but the capability to support multiple operations deteriorates
Solution Approach 1:
The design merges the functionality of separate GPP and DSP multipliers into a single unified multiplier structure. The same multiplier circuit generates partial products that are then routed to different adder arrays based on the operation type. The combiner unit merges results from these adder arrays to produce the final output. This merging approach reduces the total number of hardware components needed compared to having separate dedicated multipliers for each operation type, thereby simplifying manufacturing while maintaining full operational capability.
Data Source
AI summary
The present invention provides processing systems, apparatuses, and methods that support both general processing processor (GPP) and digital signal processor (DSP) features, such as vector and single value multiplication. In an embodiment, fractional arithmetic, integer arithmetic, saturation, and single instruction multiple data (SIMD) operations such as vector multiply, multiply accumulate, dot-product accumulate, and multiply-subtract accumulate are supported. In an embodiment, the process core and/or multiplier multiplies vector values or single values by creating partial products for each desired product. These partial products are added to produce intermediate results, which are combined in different ways to support various GPP and DSP operations.