Digital Processor Division Using Power-of-Two Approximations
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Solution Overview
Problem
Existing digital circuits for division and multiplication are costly and complex, making them inefficient for low-cost, high-performance applications, especially in control and DSP components, where sequential approaches either consume too many clock cycles or require additional resources.
Innovation Solution
A method using power-of-two approximating values to perform division and multiplication by shifting bit signals, producing approximate results that average to precise outcomes over time, reducing silicon area, power consumption, and eliminating the need for additional clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If sequential subtraction approach is used for division, then cost is reduced, but performance deteriorates due to excessive clock cycles
Solution Approach 1:
The patent applies periodic action by alternating between two different approximation sequences (first and second power-of-two approximating values) in a periodic manner. This allows the system to accumulate results over multiple periods, where the average converges to the precise division result. The periodic switching between approximations enables both low cost (simple shift operations) and acceptable performance (averaging effect over time).
Solution Approach 2:
The patent changes parameters by using power-of-two approximating values instead of exact divisor values. By representing the divisor as nearby power-of-two values (which can be implemented as simple bit shifts), the system transforms complex division into simple shift and add operations. The parameter change from exact to approximate values, combined with averaging over periodic sequences, resolves the contradiction between simplicity and accuracy.
2Productivity
If combinatorial non-restoring divider is used, then performance is improved, but device complexity increases
Solution Approach 1:
The patent segments the division operation into multiple simpler approximation operations. Instead of implementing a single complex non-restoring divider, the system segments the problem into repeated simple shift-and-add operations using power-of-two approximating values. This segmentation transforms a high-complexity single-step operation into multiple low-complexity steps, reducing overall device complexity while maintaining performance through the averaging effect.
3Ease of manufacture
If repeated addition is used for multiplication, then cost is reduced, but time consumption increases
Solution Approach 1:
The patent applies periodic action to multiplication by alternating between two power-of-two approximating values (one slightly less than the true multiplier, one slightly more). The periodic switching creates an averaging effect where the accumulated result converges to the precise multiplication result. This allows the system to use simple shift and add operations (low cost) while achieving accurate results through the periodic approximation strategy.
Solution Approach 2:
The patent changes the multiplication parameter from exact multiplier to power-of-two approximating values. By representing the multiplier as nearby power-of-two values, the system transforms complex multiplication into simple shift and add operations. The parameter change enables low-cost implementation while the averaging over periodic sequences ensures accurate results, resolving the time-cost contradiction.
Data Source
AI summary
A digital processor, such as, e.g., a divider in a PID controller, performs a mathematical operation such as division (or multiplication) involving operands represented by strings of bit signals and an operator to produce an operation result. The processor is configured by identifying first and second power-of-two approximating values of the operator as the nearest lower and nearest higher power-of-two values to the operator. The operation is performed on the input operands by means of the first and second power-of-two approximating values of the operator by shifting the bit signals in the operands by using the first and second power-of-two approximating values in an alternated sequence to produce: first approximate results by using the first power-of-two approximating value, second approximate results by using the second power-of-two approximating value. The average of the first and second approximate results is representative of the accurate result of the operation.