Processor IP Register Save/Restore via Packet Merging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing mechanisms for saving and restoring register contents in IP blocks of a processor incur significant latency due to the time-consuming process of sending individual register data packets, leading to increased entry and exit latency in low power operating modes, which affects computing system performance.
Innovation Solution
The solution involves saving and restoring register contents on a per IP block basis, eliminating the need for a dedicated ROM to store register addresses and reducing communication overhead by concatenating register data into a single packet for transmission, thereby reducing latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If individual register data packets are sent for saving and restoring contents, then data can be saved and restored, but the process incurs significant latency and increases entry/exit latency in low power modes
Solution Approach 1:
The patent combines multiple individual register data packets into a single aggregated packet for transmission. Instead of sending and receiving separate packets for each register, the system consolidates all register contents into one packet, dramatically reducing the number of communication transactions and associated latency during entry and exit from low power modes.
Solution Approach 2:
The patent performs preliminary actions by pre-identifying and pre-grouping all register contents that need to be saved before entering low power mode. The system prepares the aggregated packet in advance, so that when power state transitions are required, the save and restore operations can execute quickly without iterative communication overhead.
2Device complexity
If a dedicated ROM is used to store register addresses, then register data can be managed, but the ROM size increases and communication overhead increases
Solution Approach 1:
The patent extracts the register address storage function from the dedicated ROM and relocates it to a compact lookup table implemented in logic. This extraction eliminates the need for large dedicated ROM structures while maintaining the ability to track and manage register addresses efficiently.
Solution Approach 2:
The patent creates a simplified copy of the register address management functionality using a compact lookup table in logic rather than a full dedicated ROM. This copy retains the essential address-to-register mapping capability while occupying minimal space and requiring no extensive communication protocols.
3Quantity of substance
If individual register packets are transmitted, then each register can be saved/restored, but sideband network congestion increases
Solution Approach 1:
The patent merges multiple individual register packets into a single aggregated packet for transmission over the sideband network. This consolidation reduces the total number of packets from potentially dozens or hundreds of individual register packets to just one aggregated packet, eliminating network congestion while preserving all necessary data.
Data Source
Figure 1
Figure 2
Figure 3~5
AI summary
Described is an apparatus which comprises: an Intellectual Property (IP) block; control logic operable to send a first command to the IP block to cause the first IP block to enter a first power state from a second power state; and a communicating fabric coupled to the IP block and to the control logic, the communicating fabric to send multiple packets with a first header from the IP block to the control logic after the first command is processed by the IP block, wherein the multiple packets are associated with multiple registers which are identified as registers whose contents are to be saved.