Processor Repair via Delay Stage Switching for Fixed Transmission Time
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Solution Overview
Problem
In high-volume data processing applications, particularly in machine intelligence, there is a need for a mechanism to prevent code on one processing unit from executing ahead of dependent data from another unit, and to efficiently repair faulty processing units within a multitile processor chip to maintain functionality and yield.
Innovation Solution
A processor architecture with a fixed transmission time for messages between processing units, utilizing an exchange fabric and delay stages with switching circuitry to manage message exchange and logical identities, allowing for selective switching to repair defective units while preserving communication latency, enabling the repair of faulty processing units without disrupting the entire chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a repairing processing circuit is activated to replace a defective processing circuit, then the chip functionality is restored, but the fixed transmission time message exchange is disrupted
Solution Approach 1:
The patent introduces delay stages with variable delay parameters that can be dynamically adjusted. When a processing circuit is repaired or replaced, the delay stages in the communication paths are reconfigured to compensate for position changes, maintaining the fixed transmission time property despite physical repositioning of processing circuits.
Solution Approach 2:
The exchange fabric acts as an intermediary between processing circuits, introducing controllable delay stages that mediate the message transmission timing. These delay stages compensate for position variations caused by circuit repairs, ensuring that the overall transmission time remains fixed and predictable.
2Productivity
If manufacturing errors occur in processing circuits, then chip yield is reduced, but the complexity of repair mechanisms increases
Solution Approach 1:
The system employs dynamic reconfiguration capabilities where processing circuits can be dynamically activated or deactivated based on functional status. Switching circuitry enables runtime adjustment of circuit activation, allowing defective circuits to be bypassed and functional circuits to be reassigned without physical repositioning.
Solution Approach 2:
The patent utilizes reconfigurable delay stages and switching circuitry that can be programmed to change their operational parameters. This allows the system to adapt to different chip configurations resulting from manufacturing variations, maintaining fixed transmission time properties despite changes in which specific circuits are active.
3Reliability
If processing circuits are repositioned to repair defects, then faulty units are replaced, but communication latency varies
Solution Approach 1:
Variable delay stages are introduced in the communication paths with adjustable delay parameters. When processing circuits are repositioned or reassigned, the delay stages are reconfigured to compensate for the changed physical distances, ensuring that the overall message transmission time remains fixed and predictable.
Solution Approach 2:
The exchange fabric incorporates delay stages as intermediary elements that actively manage transmission timing. These delay stages absorb the variability introduced by circuit repositioning, maintaining consistent end-to-end latency despite changes in the physical layout or assignment of processing circuits.
Data Source
AI summary
A processor comprises a plurality of processing units, wherein there is a fixed transmission time for transmitting a message from a sending processing unit to a receiving processing unit, based on the physical positions of the sending and receiving processing units in the processor. The processing units are arranged in a column, and the fixed transmission time depends on the position of a processing circuit in the column. An exchange fabric is provided for exchanging messages between sending and receiving processing units, the columns being arranged with respect to the exchange fabric such that the fixed transmission time depends on the distances of the processing circuits with respect to the exchange fabric. The processor comprises at least one delay stage for each processing circuit and switching circuitry for selectively switching the delay stage into or out of a communication path involved in message exchange. For processing circuits up to a defective processing circuit in the column, the delay stage is switched into the communication path, and for processing circuits above the defective processing circuit in the column, including a repairing processing circuit which repairs the defective processing circuit the delay stage is switched out of the communication path whereby the fixed transmission time of processing circuits is preserved in the event of a repair of the column.