Processor Repair via Logical Identity Switching and Delay Stages
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Solution Overview
Problem
In high-volume data processing applications, particularly in machine intelligence, there is a need for a mechanism to prevent code on one processing unit from executing ahead of dependent data from another unit, and existing technologies lack an efficient repair method for defective processing units in multi-tile processors, leading to discarded chips and reduced yield.
Innovation Solution
A processor architecture with a fixed transmission time for messages between processing units, utilizing an exchange fabric and delay stages to maintain latency, and a repair mechanism where a repairing processing unit takes on the logical identity of a defective one, allowing for selective switching of delay stages to preserve transmission times during repair.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of repair
If a repairing processing unit takes on the logical identity of a defective one, then the defective unit can be repaired and reused, but the fixed transmission time based on physical positions may be disrupted
Solution Approach 1:
Delay stages are introduced as intermediary elements in the communication paths between processing units. These delay stages act as mediators that compensate for the timing disruptions caused by repair operations, ensuring that the fixed transmission time requirement is maintained even when a repairing processing unit assumes the logical identity of a defective one.
Solution Approach 2:
The system dynamically adjusts the delay parameter of communication paths by selectively switching delay stages into or out of the path. When a repair is performed and a processing unit takes on a different logical identity, the delay parameter is changed to compensate for the physical position difference, thereby maintaining the fixed transmission time requirement.
2Manufacturing precision
If delay stages are added to preserve fixed transmission time during repair, then transmission time accuracy is maintained, but device complexity increases
Solution Approach 1:
The delay stages are designed to be dynamically switchable rather than permanently fixed in the communication path. The switching circuitry allows the delay stages to be selectively engaged or disengaged based on whether a repair is active, enabling the system to adapt its complexity only when needed while maintaining the fixed transmission time property.
Solution Approach 2:
The communication path is segmented into controllable sections, with delay stages placed at specific segments that can be independently switched. This segmentation allows for granular control over when and where delays are applied, minimizing the overall impact on device complexity while still achieving the required timing precision.
3Reliability
If manufacturing errors occur in high-density tile processors, then chip functionality is compromised, but discarding the chip reduces yield
Solution Approach 1:
Instead of discarding chips with manufacturing errors, the system recovers functionality by implementing repair mechanisms that identify defective processing units and activate repairing units to assume their logical identities. This approach transforms previously discarded low-yield chips into functional processors, significantly improving chip yield while maintaining reliability.
Solution Approach 2:
The processor architecture incorporates redundant repairing processing units and delay stages as preemptive measures before manufacturing errors can compromise the entire chip. These cushioning elements are built into the design in advance, allowing the system to absorb and compensate for manufacturing defects without requiring complete chip rejection.
Data Source
AI summary
A processor comprises a plurality of processing units, wherein there is a fixed transmission time for transmitting a message from a sending processing unit to a receiving processing unit, based on the physical positions of the sending and receiving processing units in the processor. The processing units are arranged in a column, and the fixed transmission time depends on the position of a processing circuit in the column. An exchange fabric is provided for exchanging messages between sending and receiving processing units, the columns being arranged with respect to the exchange fabric such that the fixed transmission time depends on the distances of the processing circuits with respect to the exchange fabric.