Processor Reset Trace Circuitry for Microcontroller Debugging
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Solution Overview
Problem
Modern microcontrollers lack comprehensive in-circuit debug capabilities, particularly in supporting trace functions during resets, which limits their debugging efficiency and requires external, expensive debug circuitry.
Innovation Solution
A processor device with integrated debug circuitry, including a trace module, system clock module, and reset detection unit, that allows instruction tracing through both asynchronous and synchronous resets, preventing system clock resets during debugging and recording trace information for output through an external interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a microcontroller uses a standard reset mechanism, then the system can be reset normally, but the trace module cannot record trace information during the reset process
Solution Approach 1:
The reset mechanism is segmented into two independent paths: one for the system clock module that allows resetting, and another for the trace module that prevents resetting. This is achieved by selectively connecting or disconnecting the reset signal to different modules, enabling the trace module to continue operating and recording during reset events while the rest of the system can still be reset normally.
Solution Approach 2:
A trace clock module acts as an intermediary between the system clock module and the trace module. This intermediary component receives the system clock signal and conditionally forwards it to the trace module based on reset status, allowing the trace module to maintain operation during reset events while the system undergoes reset.
2Adaptability or versatility
If external debug circuitry is used to support trace functions, then comprehensive debugging capability is achieved, but the cost and device complexity increase significantly
Solution Approach 1:
The debug and trace functionality is merged into the microcontroller's internal architecture by integrating the trace module, trace clock module, and reset detection unit within the device. This eliminates the need for external debug circuitry while providing comprehensive debugging capabilities including trace recording during reset events, breakpoints, and other debug functions.
Solution Approach 2:
The trace module is designed with multi-functionality to serve multiple debugging purposes: recording trace information during normal operation, recording during reset events, providing reset source identification, and supporting various debug modes. This universal debug core replaces multiple specialized external devices.
3Reliability
If the system clock module is reset during a reset event, then the reset is complete and thorough, but the trace module loses its clock signal and cannot record trace information
Solution Approach 1:
The clocking system is segmented into the system clock module and the trace clock module. The system clock module receives reset signals and can be reset completely, while the trace clock module is protected from reset signals through selective disconnection, ensuring it maintains its clock signal and continues recording trace information throughout the reset process.
Data Source
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AI summary
A processor device with debug capabilities has a central processing unit, debug circuitry including a trace module, a system clock module for providing internal clock signals, and a reset detection unit which during a debug mode prevents the system clock module from receiving a reset signal.