Processor Performance State Control via Threshold Logic
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Solution Overview
Problem
Current processor performance state control systems in information handling systems are inefficient due to frequent transitions between low power sleep and active states, leading to unnecessary resource usage and time delays in P-state changes, especially under bursty workloads.
Innovation Solution
A hardware-based performance state control system that includes a processor and a voltage regulator, with a logic circuit that detects the processor's operating state and executes a performance state determination algorithm only when the processor stays in an active state for a predetermined threshold time, minimizing unnecessary P-state changes and optimizing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the processor enters low power sleep states frequently, then power consumption is reduced, but code execution capability is lost and time delays occur due to frequent state transitions
Solution Approach 1:
The system performs preliminary action by executing the performance state determination algorithm during the C0 state before transitioning to sleep states. This allows P-state optimization to be prepared in advance, so that when the processor does enter sleep states, the transitions are more efficient and less frequent, reducing both power consumption and execution delays.
Solution Approach 2:
The system implements periodic action by monitoring processor state transitions and executing the P-state determination algorithm at specific intervals (when C0 duration exceeds threshold). This periodic execution optimizes the balance between maintaining code execution capability and reducing power consumption, rather than continuously adjusting states.
2Productivity
If software algorithms run frequently to adjust P-states, then processor performance is optimized, but actual work producing code execution is displaced
Solution Approach 1:
The system applies partial action by executing the P-state determination algorithm only when the processor remains in the C0 state for a duration exceeding a predefined threshold. This selective execution avoids the overhead of frequent algorithm runs while still achieving performance optimization at critical moments, thus preserving code execution time.
Solution Approach 2:
The system enables self-service by having the processor automatically monitor its own C0 state duration and trigger the P-state determination algorithm when appropriate thresholds are met. This self-monitoring mechanism reduces the need for external software intervention and minimizes displacement of productive code execution.
3Speed
If the processor stays in active C0 state for short periods, then responsiveness is maintained, but P-state optimization becomes ineffective due to frequent transitions
Solution Approach 1:
The system changes the parameter of algorithm execution timing from a fixed periodic schedule to a dynamic threshold-based trigger. By monitoring C0 state duration and executing the P-state determination algorithm only when this duration exceeds a predefined threshold, the system adapts to varying workload patterns and maintains both responsiveness and optimization effectiveness.
Data Source
AI summary
A performance state control system includes a processor and a voltage regulator coupled to the processor. The voltage regulator provides a regulated voltage to the processor, as instructed by the processor. A logic circuit coupled to the processor and the voltage regulator detects that the processor is in an operating power state, determines a time that the processor is in the operating state and instructs the processor to execute a performance state determination algorithm when the time that the processor is in the operating state exceeds a pre-determined threshold value.