Processor Voltage Regulation With DFLL Response to Voltage Droop
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Solution Overview
Problem
CMOS integrated circuits face power consumption issues due to voltage droop, which can lead to circuit failure, as existing power management mechanisms are inadequate in responding quickly and accurately to sudden changes in load, especially with bursty processing workloads.
Innovation Solution
A data processing system that includes a data processor and a voltage regulator, where the data processor automatically reduces the clock signal frequency during a voltage droop using an adaptive digital frequency locked loop (DFLL) and communicates with the voltage regulator to set desired voltage-current relationships, ensuring continued operation at lower voltages and rapid recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the power supply voltage is reduced to lower power consumption, then energy efficiency improves, but voltage droop increases causing circuit failure
Solution Approach 1:
The patent implements dynamic voltage and frequency adjustment by transitioning between different P-states (performance states) based on real-time processing needs. The system dynamically selects operating points that balance power consumption and voltage stability, using an adaptive DFLL to continuously monitor and adjust frequency in response to voltage droop conditions, enabling the system to operate at lower voltages without causing circuit failure.
Solution Approach 2:
The system employs a feedback mechanism where the adaptive DFLL continuously monitors the actual clock frequency and compares it against the target frequency. When voltage droop causes frequency deviation, the DFLL generates correction signals that adjust the voltage regulator's output, creating a closed-loop control system that maintains reliable operation while allowing voltage reduction for power savings.
2Productivity
If the frequency is increased to improve processing performance, then productivity improves, but voltage droop becomes more severe
Solution Approach 1:
The system dynamically adjusts operating parameters by implementing P-state transitions that coordinate voltage and frequency changes. When high processing performance is needed, the system transitions to higher P-states with increased frequency and voltage. The adaptive DFLL continuously monitors frequency accuracy and provides real-time adjustments to prevent voltage droop from causing circuit failure during high-performance operation.
Solution Approach 2:
The patent changes operating parameters (voltage and frequency) by transitioning between discrete P-states. Each P-state represents a specific combination of voltage and frequency settings optimized for different performance requirements. The system selects appropriate P-states based on processing needs while the adaptive DFLL ensures frequency accuracy is maintained, preventing voltage droop from compromising reliability during high-frequency operation.
3Device complexity
If existing power management mechanisms are used, then device complexity is minimized, but response time to voltage droop is too slow
Solution Approach 1:
The patent combines the voltage regulation function with an adaptive digital frequency-locked loop (DFLL) that directly controls the phase-locked loop (PLL) frequency. This merged architecture eliminates the need for separate slow power management response mechanisms, as the DFLL provides rapid frequency adjustment in direct response to voltage droop detection. The integration of frequency control with voltage regulation creates a unified fast-response system that maintains simplicity while dramatically improving response time.
Solution Approach 2:
The adaptive DFLL acts as an intermediary between the voltage regulator and the processing circuitry. It rapidly detects voltage droop effects on clock frequency and translates these into corrective frequency adjustments, serving as a fast mediator that bridges the gap between power supply variations and processor operation. This intermediary function provides rapid response without requiring complex power management hardware.
Data Source
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AI summary
A data processor includes at least one power supply voltage terminal for receiving a power supply voltage and a power supply current, a data processing circuit, a register, and a port controller. The data processing circuit is coupled to the at least one power supply voltage terminal and operates using the power supply voltage. The register stores a nominal value of the power supply voltage, an electrical design current (EDC) limit, and an EDC slope, wherein the EDC slope specifies a desired voltage-current relationship for an external voltage regulator when the power supply current exceeds the EDC limit. The port controller is coupled to the register and to an output port. The data processing circuit is operative to cause the port controller to output the nominal value of the power supply voltage, the EDC limit, and the EDC slope over the output port for use by the external voltage regulator.