Profiled Metal Gate Structure for Uniform CMOS Threshold Voltage
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Solution Overview
Problem
Complementary metal-oxide-semiconductor (CMOS) technology relies on doped polysilicon gate electrodes, which have limitations in achieving optimal work-function profiles for NMOS and PMOS transistors, leading to suboptimal performance and efficiency.
Innovation Solution
The implementation of a semiconductor device with a metal gate electrode structure that includes a profiled work-function metal gate, comprising a high-k gate dielectric layer, a barrier layer, an intermediate work-function metal layer, and a work-function adjustment layer, formed through a series of deposition and annealing processes to achieve a crystalline work-function metal layer with ordered grain orientation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If doped polysilicon gate electrodes are used in CMOS technology, then the device structure is simple and manufacturing is easier, but the work-function profile cannot be optimized for NMOS and PMOS transistors, leading to suboptimal performance
Solution Approach 1:
The gate electrode is segmented into multiple distinct layers: a base metal layer (titanium, tungsten, or tantalum), an intermediate metal layer (titanium aluminide, nickel aluminide, or iron aluminide), and a work-function adjustment layer (aluminum, tungsten, copper, or cobalt). This segmentation allows each layer to contribute differently to the overall work-function profile, enabling independent optimization for NMOS and PMOS transistors while maintaining manufacturing feasibility through sequential deposition processes
Solution Approach 2:
The gate electrode employs a composite material structure combining multiple metals with different work functions. The base metal layer provides structural stability, the intermediate metal layer contributes to work-function modulation, and the work-function adjustment layer fine-tunes the electrical characteristics. This composite approach enables achieving optimal work-function profiles for both NMOS and PMOS devices within a unified gate structure, resolving the contradiction between performance optimization and structural simplicity
2Productivity
If a uniform metal gate structure is used, then manufacturing is simplified, but resistance between source and drain extensions increases, reducing device efficiency
Solution Approach 1:
The gate electrode structure implements local quality variations through its layered composition. The work-function adjustment layer is specifically engineered to reduce resistance between source and drain extensions by providing a low-resistance pathway in critical regions. The intermediate metal layer is configured with specific thickness and composition (titanium aluminide, nickel aluminide, or iron aluminide) to locally optimize electrical characteristics without compromising the overall gate structure integrity, thereby improving device efficiency while maintaining manufacturing simplicity through a standardized multi-layer deposition process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the semiconductor device's performance by providing a uniform threshold voltage and improved drain current, reducing resistance between source and drain extensions, and overcoming the limitations of doped polysilicon gate electrodes.
Implementation Method 1
a post thermal anneal is performed to convert the intermediate work-function metal layer to a work-function metal layer
Implementation Method 2
achieve a crystalline work-function metal layer with ordered grain orientation
Data Source
AI summary
The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.