16-bit Program Counter Memory Expansion Without Bank Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing computing devices face challenges in expanding memory space without increasing circuit complexity and deteriorating instruction efficiency, particularly due to the need for memory bank switching.
Innovation Solution
A computing device design that utilizes a 16-bit program counter to read instructions from a program memory with a first and second memory area, where the least significant bit of the program counter determines the target memory area, allowing for expanded memory space without memory bank switching, maintaining instruction efficiency and compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory bank switching is used to expand memory space, then memory space is expanded, but circuit scale increases and instruction efficiency deteriorates
Solution Approach 1:
The program memory is segmented into multiple banks (first bank and second bank), each accessible through a different mode. By dividing the memory into segments that can be independently accessed, the system expands total memory capacity without requiring complex switching circuitry, as each bank can be accessed directly based on the mode signal.
Solution Approach 2:
The patent introduces a mode dimension (first mode and second mode) to access different memory banks. Instead of using complex bank switching circuits, the system adds a modal dimension to address selection, where the same address bus can access different physical memory locations depending on the current mode, effectively expanding memory space without increasing circuit complexity.
2Quantity of substance
If memory bank switching is used to expand memory space, then memory space is expanded, but instruction efficiency deteriorates
Solution Approach 1:
The system pre-establishes two distinct access modes (first mode and second mode) that directly map to different memory banks. This preliminary configuration allows the processor to access expanded memory space without requiring runtime bank switching operations, as the mode is set in advance and remains stable during instruction execution, thereby maintaining high instruction efficiency.
Solution Approach 2:
The same address bus and control logic are made multi-functional by allowing them to operate in two different modes. The address bus can simultaneously serve both memory banks depending on the active mode, eliminating the need for dedicated switching circuitry and preserving instruction execution speed while accessing expanded memory space.
3Quantity of substance
If 16-bit program counter is used with upper 15-bit address specification, then memory space is expanded to 128kB, but address mapping complexity increases
Solution Approach 1:
The mode signal acts as an intermediary that simplifies address mapping. Instead of requiring complex logic to map 16-bit program counter values to 128kB memory space, the mode signal mediates between the program counter and the two 64kB memory banks, allowing simple direct mapping within each bank while the mode selects which bank is active, thereby reducing address mapping complexity.
Data Source
AI summary
The present disclosure relates to a computing device. A computing device includes an arithmetic processing circuit configured to execute a program, and a program memory for storing the program. Each instruction in the program has a length of 16 bits. The program memory has a first memory area, and a second memory area in which higher addresses than the first memory area are associated. The arithmetic processing circuit has a 16-bit program counter for specifying an address to be read, and reads and executes an instruction at an address corresponding to an upper 15-bit value of the program counter from a target memory area, wherein the target memory area is, of the first memory area and the second memory area, a memory area corresponding to a value of a least significant bit in the program counter.