Programmable Accelerator Architecture for Irregular Memory-Bound Operations
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Solution Overview
Problem
Existing accelerators are highly specialized and inefficient for data-dependent, irregular, and memory-bound operations due to unpredictable computational loads and memory access patterns, leading to performance bottlenecks and inefficient resource utilization.
Innovation Solution
A programmable accelerator with a tiled processor architecture, including a vector core, cross-lane processing unit, and shared scratchpad memory, capable of dynamically adapting to data-dependent and memory-bound operations through features like cooperative prefetching, stream instructions, and scatter-gather engines, allowing flexible configuration and high-bandwidth data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If accelerators are designed to be highly specialized for specific operations, then acceleration efficiency for those operations is improved, but adaptability to different operation types deteriorates
Solution Approach 1:
The accelerator is designed with a universal architecture that can perform multiple types of operations including data-dependent operations, irregular operations, and memory-bound operations through a single programmable engine, eliminating the need for separate specialized accelerators for each operation type
Solution Approach 2:
The accelerator employs dynamic reconfiguration capabilities where the programmable engine can adapt its behavior and resource allocation based on the specific operation being executed, allowing it to optimize performance for different operation types without physical redesign
2Ease of manufacture
If accelerators use predetermined designs for specific operation classes, then manufacturing complexity is reduced, but ability to handle data-dependent operations deteriorates
Solution Approach 1:
A single accelerator design incorporates a programmable engine that can be configured at runtime to handle data-dependent operations, eliminating the need to manufacture different accelerator variants for different operation types while maintaining ease of fabrication
Solution Approach 2:
The accelerator uses parameter-based configuration where operation characteristics such as computational load and memory access patterns are specified through parameters rather than hard-coded design, allowing the same hardware to adapt to varying operation requirements
3Device complexity
If accelerators rely on non-accelerated devices to perform irregular operations, then accelerator design complexity is reduced, but overall system performance deteriorates due to memory bandwidth stress and delays
Solution Approach 1:
The accelerator incorporates a programmable engine capable of handling irregular operations including those with unpredictable memory access patterns, allowing the accelerator to perform a broader range of operations without requiring additional non-accelerated devices, thus improving overall system performance
4Productivity
If accelerators are designed for regular operations with predictable computational loads, then resource utilization is optimized, but flexibility to adapt to varying computational requirements deteriorates
Solution Approach 1:
The accelerator employs dynamic resource allocation where computational resources are allocated and configured based on the specific operation's requirements rather than being statically fixed, allowing efficient resource utilization across different operation types with varying computational demands
Data Source
AI summary
Aspects of the disclosure provide for an accelerator capable of accelerating data dependent, irregular, and/or memory-bound operations. An accelerator as described herein includes a programmable engine for efficiently executing computations on-chip that are dynamic, irregular, and/or memory-bound, in conjunction with a co-processor configured to accelerate operations that are predictable in computational load and behavior on the co-processor during design and fabrication.