Programmable Charge-Storage Transistor With Ferroelectric Gate
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Solution Overview
Problem
Current programmable charge-storage transistors and memory cell arrays face challenges in achieving efficient programming and erasing operations due to limitations in voltage requirements and retention times, particularly in achieving faster and more reliable data storage in non-volatile memory systems.
Innovation Solution
The implementation of a programmable charge-storage transistor design featuring a gate construction with a combination of insulative charge-passage material, charge-storage material, and charge-blocking material, where the charge-blocking material comprises a non-ferroelectric insulator and a ferroelectric insulator, allowing for efficient charge management and retention, and the formation of arrays of elevationally-extending strings of memory cells with vertically-stacked tiers for enhanced data storage capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional charge-storage transistor designs are used, then manufacturing is simpler, but programming and erasing speeds are slower and retention times are shorter
Solution Approach 1:
The gate construction is segmented into multiple functional layers: a first charge-blocking material layer, a charge-storage material layer, a charge-passage material layer, and a second charge-blocking material layer. Each layer performs a specific function in charge management, enabling faster programming/erasing while maintaining structural organization that simplifies manufacturing processes.
Solution Approach 2:
The gate construction uses composite materials with different electrical properties arranged in specific layers. The charge-blocking materials (insulators) prevent charge leakage, the charge-storage material retains charge, and the charge-passage material allows controlled charge movement. This composite structure optimizes both speed and retention while remaining compatible with existing manufacturing techniques.
2Speed
If higher programming and erasing voltages are applied, then programming and erasing speeds improve, but energy consumption increases
Solution Approach 1:
The patent optimizes the electrical parameters of each gate layer to achieve efficient charge injection and retention. The charge-passage material layer is designed with specific thickness and conductivity to allow rapid charge movement at lower voltages, while the charge-blocking layers prevent leakage, reducing the need for high voltage maintenance and lowering overall energy consumption.
Solution Approach 2:
The charge-passage material layer acts as an intermediary between the charge-storage material and the control gate. It facilitates controlled charge transfer during programming and erasing operations, enabling efficient charge manipulation at reduced voltage levels compared to direct charge injection methods.
3Duration of action of stationary object
If charge retention time is extended, then data reliability improves, but programming and erasing time increases
Solution Approach 1:
Different regions of the gate construction have specialized properties optimized for specific functions: the charge-storage material layer provides long-term retention capability, while the charge-passage material layer enables rapid charge injection during programming. This local optimization allows simultaneous achievement of fast programming and long retention without compromise.
Solution Approach 2:
The charge-blocking material layers are positioned to prevent charge leakage before it can occur, providing a protective barrier that maintains data integrity over extended periods. This preemptive charge containment ensures long retention times without requiring prolonged programming durations to achieve the same reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables faster programming and erasing processes while improving data retention times, leading to more efficient and reliable non-volatile memory operations, particularly in flash memory applications.
Implementation Method 1
The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material
Implementation Method 2
charge-storage material, where the charge-blocking material comprises a non-ferroelectric insulator and a ferroelectric insulator, allowing for efficient charge management and retention
Implementation Method 3
A conductive gate is adjacent the channel region and separated there-from by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region.
Data Source
AI summary
A programmable charge-storage transistor comprises channel material, insulative charge-passage material, charge-storage material, a control gate, and charge-blocking material between the charge-storage material and the control gate. The charge-blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material. Arrays of elevationally-extending strings of memory cells of memory cells are disclosed, including methods of forming such. Other embodiments, including method, are disclosed.