Programmable Clock Input Filter for Glitch Rejection and Duty Cycle Control
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Solution Overview
Problem
Existing clock input filter circuits are large, consume significant static power, and lack programmability to adjust the duty cycle of output signals, making them inefficient and inflexible for integrated circuit applications.
Innovation Solution
A clock input filter circuit utilizing programmable low-pass delay elements to filter input signals during both low and high periods, with output multiplexing to adjust duty cycles, and consuming minimal static power by eliminating analog differential comparators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog differential comparators are used in clock input filter circuits, then filtering capability is improved, but static power consumption increases significantly
Solution Approach 1:
The patent replaces analog differential comparators with a digital logic-based filtering mechanism using delay elements and logic gates. This substitution eliminates the need for continuous analog comparison operations that consume static power, while achieving equivalent glitch filtering through digital signal processing techniques.
Solution Approach 2:
The filtering is achieved through periodic sampling and delay-based techniques rather than continuous analog comparison. The digital logic circuit processes clock signals in discrete periods, reducing overall power consumption while maintaining filtering effectiveness for glitch removal.
2Device complexity
If fixed delay circuits are used in clock input filters, then circuit simplicity is improved, but adaptability to adjust duty cycle is lost
Solution Approach 1:
The patent implements programmable delay elements that can be dynamically configured to adjust the filtering characteristics and duty cycle of output signals. This dynamic configurability allows the same circuit structure to adapt to different operating conditions and signal requirements without increasing fundamental circuit complexity.
Solution Approach 2:
The delay elements are designed to serve multiple functions: glitch filtering, duty cycle adjustment, and signal conditioning. This multi-functionality allows a single circuit configuration to handle various clock signal requirements, enhancing adaptability without proportionally increasing circuit complexity.
3Area of stationary object
If integrated circuit form is used for clock input filters, then miniaturization is improved, but static power consumption increases
Solution Approach 1:
The patent replaces power-hungry analog comparator circuits with digital logic implementations that consume less static power. This substitution enables compact integrated circuit design while maintaining lower power consumption characteristics, as digital logic can be more efficiently implemented in standard CMOS processes.
Data Source
AI summary
A clock input filter uses a first programmable low-pass delay element to filter during a low period of an input clock signal and to output a SET signal. The clock input filter uses a second programmable low-pass delay element to filter during a high period of the input clock signal and to output a RESET signal. A latch is set and reset by the SET and RESET signals. The latch outputs a filtered version of the input signal that has the same approximate duty cycle as the input signal. A pair of gates generates a corresponding pair of duty cycle adjusted versions of the input signal. Output multiplexing circuitry is provided to output either the output of the latch, or an increased duty cycle version of the input signal, or a decreased duty cycle version of the input signal, or an unfiltered version of the input signal.