Programmable Delay Circuit for Glitch-Free Delay Switching
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Solution Overview
Problem
Programmable delay circuits in DDR systems face issues with glitches when the delay setting is changed, leading to system downtime and increased power consumption due to complex control circuitry, and are restricted to changing delay settings in steps of one.
Innovation Solution
A programmable delay circuit design that prevents glitches by using a series of delay stages with NAND and NOR gates and multiplexers, allowing for any delay setting change in one clock cycle without complex control circuitry, maintaining static output logic states during changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex control circuitry is used to prevent glitches when changing delay settings, then reliability is improved, but power consumption increases and device complexity increases
Solution Approach 1:
The patent extracts and eliminates the complex control circuitry from the delay element design. By using a simple latch-based structure without elaborate control logic, the invention removes the source of high power consumption while maintaining glitch-free operation through the inherent behavior of the latch circuit during signal transitions.
Solution Approach 2:
The latch circuit automatically maintains stable output logic states during signal transitions without requiring external control signals or complex control circuitry. The circuit self-regulates its behavior during delay setting changes, preventing glitches inherently through its design rather than through active control mechanisms.
2Reliability
If complex control circuitry is used to prevent glitches when changing delay settings, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent removes complex control circuitry from the delay element design, retaining only simple latch-based structures. This extraction eliminates the complexity issue while preserving glitch prevention capabilities through the straightforward latch mechanism that naturally maintains stable states during transitions.
Solution Approach 2:
Instead of using complex control circuitry to actively prevent glitches, the invention inverts the approach by designing a circuit that inherently produces no glitches through its simple latch structure. The solution goes from active control to passive inherent stability, eliminating complexity while maintaining reliability.
3Ease of manufacture
If traditional delay circuits are used, then manufacturing is simplified, but delay settings can only be changed in steps of one
Solution Approach 1:
The latch-based delay element provides dynamic and continuous delay adjustment capability, allowing delay settings to be changed by any amount rather than in fixed steps. This dynamic behavior is achieved through the latch circuit's ability to respond to any change in select signals, providing versatile delay control while maintaining manufacturing simplicity.
Data Source
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AI summary
Programmable delay circuits are described herein according to embodiments of the present disclosure. In one embodiment, a delay circuit comprises a plurality of delay stages coupled in series. Each of the delay stages comprises a delay gate on a forward path of the delay circuit, wherein the delay gate is configured to pass or block a signal on the forward path depending on a logic state of a respective select signal. Each of the delay stages also comprises a multiplexer on a return path of the delay circuit, wherein the multiplexer is configured to pass a signal on the return path or route the signal on the forward path to the return path depending on the logic state of the respective select signal. Output logic states of the delay gates and the multiplexers may remain static during a change in the delay setting of the delay circuit to reduce glitch