Programmable DFE Equalization Stages for Serial Signal Distortion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed serial interfaces face challenges in maintaining accurate data transmission due to signal losses, with pre-emphasis being costly and decision feedback equalization requiring expensive and power-intensive engines, especially for lower-cost receivers.
Innovation Solution
A programmable multi-stage equalization circuit with decision feedback equalization stages that apply gain to high-frequency components and adjust the data signal based on distortion caused by preceding bits, using programmable current sources and load resistors to compensate for intersymbol interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If pre-emphasis is used to compensate for signal losses, then signal amplitude is improved, but high frequency components couple undesirably to other circuitry
Solution Approach 1:
The patent extracts the equalization function from the transmitter to the receiver side. Instead of applying pre-emphasis at the transmitter that boosts all frequency components including harmful high frequencies, the equalization is performed at the receiver where only the necessary frequency compensation is applied without generating the harmful high frequency coupling in the first place
Solution Approach 2:
The patent introduces an intermediary equalization stage at the receiver that mediates between the degraded signal from the transmission medium and the decision circuitry. This equalization stage restores the signal quality without requiring the transmitter to apply aggressive pre-emphasis that causes high frequency coupling issues
2Reliability
If decision feedback equalization is implemented to compensate for intersymbol interference, then data transmission accuracy is improved, but implementation cost and power consumption increase
Solution Approach 1:
The patent segments the equalization function into multiple simpler stages rather than implementing a single complex decision feedback equalization engine. By dividing the equalization task across multiple stages with simpler circuitry each, the overall system achieves the needed interference compensation without requiring a costly and power-intensive single-stage DFE engine
Solution Approach 2:
The patent employs programmable current sources that can be dynamically configured to provide the appropriate equalization characteristics. This dynamic programmability allows the equalization circuit to adapt to different transmission conditions and achieve optimal performance with simpler, more cost-effective circuitry compared to fixed complex DFE engines
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively compensates for signal distortion across multiple preceding bits, improving bit error rates and enabling accurate high-speed data transmission without the need for expensive engines, making it suitable for lower-cost receivers.
Implementation Method 1
transistors coupled to the positive and negative ends of the output that allow a programmable current source to draw current from either the positive or negative end of the output
Implementation Method 2
The programmable current source may be programmed to produce a current that causes the voltage drop across the load resistor to be adjusted by an amount comparable to the amount of distortion caused by the preceding bit
Implementation Method 3
the equalization stage may apply a gain to the high-frequency components (e.g., the bit transitions) in the data signal
Implementation Method 4
Equalization circuitry is designed to respond strongly and rapidly to any transition detected in the received signal. This strong and rapid response restores the original steepness to these transitions
Data Source
AI summary
Equalization circuitry may be implemented by cascading a plurality of equalization stages. Each equalization stage may compensate for some of the attenuation of a received data signal. Each equalization stage may also be configured to perform decision feedback equalization to remove distortion from the current bit of data signal caused by one of the preceding bits in the data signal. Each equalization stage may be controlled by a DFE coefficient that determines the amount of voltage with which to adjust the output of the equalization stage. The equalization circuitry may be implemented on a receiver that includes clock data recovery circuitry and a pipeline/deserializer for providing preceding bit values to the equalization stages.