Programmable Die Stitching With BEOL Routing for Flexible Harvesting
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Solution Overview
Problem
Existing IC manufacturing methods face limitations in efficiently interconnecting and harvesting multiple dies from a wafer, particularly in forming die-to-die and component-to-component routing, which restricts flexibility and scalability in die set configurations.
Innovation Solution
Implementing programmable dicing techniques and die-to-die routing with partial and full metallic seals, allowing for flexible scribing of custom die sets and integration of additional units, along with BEOL build-up structures for electrical connections, to enhance wafer utilization and protect against environmental factors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional scribing methods are used to separate dies from wafer, then dies can be harvested, but flexibility in die set configurations is restricted and wafer utilization is reduced
Solution Approach 1:
The patent implements programmable dicing techniques that allow dynamic configuration of die sets based on testing results and customer requirements. The system can adaptively determine which dies to group together and how to route connections between them, transforming the static scribing process into a dynamic, reconfigurable operation that maximizes both flexibility and wafer utilization
Solution Approach 2:
The patent segments the wafer into multiple potential die sets that can be independently configured. By dividing the wafer into harvestable regions with programmable boundaries, the system enables flexible grouping of dies into custom configurations while maintaining efficient wafer utilization through optimized segmentation strategies
2Adaptability or versatility
If die-to-die routing is implemented to connect adjacent dies, then interconnection flexibility is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by pre-forming BEOL build-up structures and metallic seal patterns across the entire wafer before dicing. This allows die-to-die routing paths to be pre-established and programmed, reducing manufacturing complexity during the actual die separation process while maintaining high interconnection flexibility
Solution Approach 2:
The patent implements a universal BEOL build-up structure that serves multiple functions: it provides electrical interconnections between dies, forms metallic seals for environmental protection, and enables programmable routing configurations. This multi-functional approach reduces overall manufacturing complexity by consolidating multiple processes into a unified system
3Reliability
If metallic seals are formed to protect dies from environmental factors, then reliability is improved, but additional processing steps increase manufacturing complexity
Solution Approach 1:
The patent merges the metallic seal formation process with the BEOL build-up structure fabrication. By combining these two functions into a single integrated processing sequence, the system improves reliability through comprehensive environmental protection while minimizing the increase in manufacturing complexity through process consolidation
4Adaptability or versatility
If custom die sets are scribed with programmable dicing techniques, then adaptability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent replaces traditional mechanical scribing methods with programmable dicing techniques that use precision-controlled cutting paths. This substitution enables custom die set configurations with high adaptability while managing manufacturing precision requirements through programmable control systems that can compensate for variations and achieve accurate cuts
Data Source
AI summary
Multi-die structures with die-to-die routing are described. In an embodiment, each die is patterned into the same semiconductor substrate, and the dies may be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals may be formed to accommodate the die-to-die routing, programmable dicing, and various combinations of full metallic seals and partial metallic seals can be formed. This may also be extended to three dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.


