Programmable IC Grade Verification Against Counterfeit Relabeling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The variability in feature sizes of integrated circuits due to manufacturing processes leads to performance inconsistencies, making it challenging to ensure that programmable logic ICs meet specific speed and power efficiency requirements, and there is a risk of counterfeit re-labeling of lower-grade dies being sold as higher-grade ones, resulting in potential failures and damage to manufacturers' reputations.
Innovation Solution
A programmable integrated circuit (IC) with a configuration controller that compares die-specific performance grade values stored in non-volatile memory with those indicated in a bitstream, allowing programming only if the grades match, and preventing operation if the die-specific performance grade is lower than required, thereby restricting unauthorized use and ensuring legitimate performance levels are met.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If performance grading and sorting is implemented to match die capabilities to application requirements, then lower performing dies can be sold at discounted price for non-demanding applications, but there is a risk that packaged dies may be relabeled to indicate higher grade and wrongfully resold as legitimate packaged dies
Solution Approach 1:
The patent applies preliminary action by embedding a unique die identifier and performance grade information into the die itself during manufacturing, before packaging and sorting. This pre-encoded information serves as an immutable record that travels with the die through all subsequent handling, testing, and packaging operations. When the die is later tested and graded, the system can verify that the die's actual performance matches its pre-recorded identity, preventing relabeling of lower-grade dies as higher-grade ones. The configuration bitstream includes this die-specific information, allowing the system to authenticate that the die being programmed is the same die that was tested and graded, thus ensuring the reliability of performance grade labeling throughout the supply chain.
2Reliability
If die-specific performance grade values are stored in non-volatile memory and verified against bitstream information, then counterfeit re-labeling is prevented, but the device complexity increases due to additional verification circuitry and memory
Solution Approach 1:
The patent applies universality by designing the configuration controller to perform multiple functions: it not only programs the programmable logic with configuration data from the bitstream but also verifies the die's identity and performance grade by comparing bitstream information against data stored in non-volatile memory. This single controller handles both the legitimate configuration task and the security verification task, eliminating the need for separate dedicated verification circuitry. The non-volatile memory serves dual purposes: storing performance grade information for verification and potentially storing other device-specific configuration parameters. By consolidating these functions into existing components, the patent prevents counterfeit relabeling while minimizing the increase in device complexity.
Data Source
AI summary
In one embodiment, a method for restricting use of an integrated circuit (IC) is provided. A write-once memory of a programmable IC contains a first die-specific performance grade indicator. In response to receiving an input code having a second die-specific performance grade indicator with a value indicating a level of performance greater than or equal to a level of performance indicated by the first die-specific performance grade indicator, enabling operation of the IC. In response to receiving a configuration bitstream having the second die-specific performance grade indicator with a value indicating a level of performance less than a level of performance indicated by the first die-specific performance grade indicator, preventing operation of the IC.


