Programmable IC and Companion Die Layout for Lower-Cost SiP Bandwidth
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Solution Overview
Problem
Modern programmable devices, such as FPGAs, face increasing costs due to advanced process technology and overhead, making traditional monolithic architectures unsustainable for cost-sensitive applications, while system-in-package (SiP) solutions with expensive interposers or complex die stacking are limited to high-end applications.
Innovation Solution
An active-by-active programmable device is implemented using a multi-chip module (MCM) package with a programmable IC and companion ICs on a substrate, connected via a high-bandwidth SiP bridge that aggregates and disperses data using a protocol stack, allowing the programmable IC to use newer process technology while the companion IC uses older technology, reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional monolithic architectures are used, then all circuit blocks can benefit from new process technology, but the cost increases rapidly and becomes unsustainable for cost-sensitive applications
Solution Approach 1:
The device is divided into two separate semiconductor dies: a first die containing logic circuitry that benefits from new process technology, and a second die containing application IO circuits that can use older, less expensive process technology. This segmentation allows each die to be optimized independently for its specific function, resolving the contradiction between achieving high performance and controlling manufacturing cost.
2Speed
If system-in-package solutions with expensive interposers or complex die stacking are used, then high-bandwidth connectivity is achieved, but the added cost limits benefits to high-end applications only
Solution Approach 1:
A bridge circuit is introduced as an intermediary component that couples the first and second semiconductor dies. This bridge provides high-bandwidth connectivity between the logic circuitry and application IO circuits without requiring expensive interposers or complex three-dimensional die stacking architectures, thereby achieving high speed communication at lower cost.
Solution Approach 2:
The application IO circuits are extracted from the main programmable device die and placed on a separate second die. This extraction eliminates the need for expensive interposer substrates or complex stacking arrangements, as the separated die can be connected through simpler, more cost-effective packaging techniques while maintaining high-bandwidth connectivity.
3Adaptability or versatility
If application IO circuits are included on the programmable IC, then complete functionality is achieved, but die area is consumed and prevents use of newer process technology
Solution Approach 1:
The device functionality is segmented across two separate dies: the first die is dedicated to logic circuitry and can fully utilize newer process technology for high performance, while the second die houses application IO circuits. This segmentation resolves the area conflict by distributing different functional blocks to different substrates, allowing the main programmable device to maintain adaptability through the separate IO die while preserving die area for advanced processing.
Data Source
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AI summary
An example integrated circuit (IC) system includes a package substrate (202) having a programmable integrated circuit (IC) (101 A) and a companion IC (103A) mounted thereon, the programmable IC including a programmable fabric (404) and the companion IC including application circuitry (107A). The IC system further includes a system-in-package (SiP) bridge (144) including a first SiP IO circuit (140A) disposed in the programmable IC, a second SiP IO circuit (142) disposed in the companion IC, and conductive interconnect (138) on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits (110, 112) in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits (126, 128) in the companion IC coupled between the application circuitry and the second SiP IO circuit.