Programmable Logic Block with Flexible PLA Clock Selection
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Solution Overview
Problem
Traditional integrated circuits with programmable logic arrays (PLAs) lack flexibility in selecting clock signals, resulting in static and inflexible systems, and often offer either low complexity or high complexity, failing to provide users with adequate programmability.
Innovation Solution
A PLA that allows flexible selection of clock sources, where each logic cell can receive a global clock signal or use input signals as clock signals, with a clock selection multiplexer enabling programmers to choose the appropriate clock signal, and a programmable logic block combining simple and complex logic arrays through an interface for enhanced programmability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single global clock signal is supplied to all flip-flops in a PLA, then synchronous operation and predictable timing are achieved, but flexibility in clock selection is lost
Solution Approach 1:
The patent segments the clock distribution system by providing separate clock input terminals (global clock input and local clock inputs) to different parts of the logic cell array. This allows different regions or cells to be clocked independently, resolving the contradiction between maintaining synchronous reliability and enabling clock flexibility.
Solution Approach 2:
The patent introduces dynamic clock selection capability where the clock source for each logic cell can be programmably configured. This dynamic adaptability allows the system to switch between global and local clocking modes as needed, achieving both reliability through controlled synchronization and flexibility through reconfigurable clock sources.
2Device complexity
If traditional PLA systems use a fixed clock distribution architecture, then timing prediction is simplified, but programmability and adaptability are reduced
Solution Approach 1:
The patent implements preliminary configuration of clock selection through programmable logic cell setup. Before operation, each logic cell's clock source is predetermined through configuration, which simplifies timing analysis during operation while maintaining programming flexibility during the configuration phase.
3Device complexity
If only simple PLA or complex FPGA is provided, then device design is simplified, but user flexibility in choosing logic complexity is lost
Solution Approach 1:
The patent creates a universal programmable logic device that can function as either simple PLA or complex FPGA depending on configuration. The same physical device structure supports multiple operational modes and complexity levels, allowing users to choose appropriate logic complexity for their applications without being constrained to separate simple or complex device types.
Data Source
AI summary
An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.