Programmable Logic Interconnect for Low-Power Task Offloading
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Solution Overview
Problem
Existing programmable logic circuitry is often unnecessarily generic or complex for certain applications, leading to underutilization of circuitry, increased power consumption, and higher costs due to the need for customized hardware or active processor states for tasks like serial communication and key detection.
Innovation Solution
A programmable logic unit (PLU) architecture that includes programmable logic elements such as truth tables, decoders, counters, and filters, along with a programmable interconnect array, allowing for flexible reconfiguration and offloading tasks from the processor unit, reducing power consumption and material costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing programmable logic circuitry is used, then flexibility and adaptability are provided, but power consumption increases and circuitry is underutilized
Solution Approach 1:
The programmable logic device is divided into multiple independently configurable logic elements (LEs) that can be individually enabled or disabled. Each LE can be programmed to perform specific functions (AND, OR, NOT, XOR, etc.) and connected through programmable interconnects. This segmentation allows only the necessary logic elements to remain active, reducing overall power consumption while maintaining the required flexibility for different logic functions.
2Adaptability or versatility
If existing programmable logic circuitry is used, then adaptability is provided, but device complexity and costs increase
Solution Approach 1:
The patent employs universal logic elements that can be programmed to perform multiple logic functions (AND, OR, NOT, XOR, NAND, NOR, etc.) through configuration bits. These universal LEs replace the need for multiple dedicated logic gates, simplifying the overall device structure while maintaining high adaptability. The programmable interconnect array also provides universal routing capabilities, further reducing complexity compared to dedicated hardware designs.
3Productivity
If customized hardware or active processor states are used for tasks like serial communication and key detection, then task performance is improved, but power consumption and costs increase
Solution Approach 1:
The patent extracts specific tasks (serial communication, key detection, etc.) from the main processor and implements them in dedicated logic elements within the programmable logic device. By taking these tasks out of the processor, the processor can enter low-power states while the PLD handles the extracted functions independently, reducing overall system power consumption while maintaining task performance.
4Adaptability or versatility
If programmable logic elements are individually configured, then adaptability and reconfigurability are improved, but device complexity increases
Solution Approach 1:
The patent implements dynamically reconfigurable logic elements where the function and connectivity of each LE can be changed during operation through configuration bits. The programmable interconnect array allows dynamic routing changes, enabling the device to adapt to different logic functions and configurations as needed. This dynamic reconfigurability is achieved through systematic control mechanisms rather than static fixed connections, balancing adaptability with manageable complexity.
Data Source
AI summary
Programmable logic units are described. A described unit includes one or more input interfaces to receive one or more input signals; logic elements that are individually programmable; one or more output interfaces to provide one or more output signals; and a programmable interconnect array that is configured to selectively form one or more interconnections within the unit based on one or more programming settings. The programmable interconnect array can be programmable to route the one or more input signals from the one or more input interfaces to at least a portion of the logic elements, programmable to route one or more intermediate signals among at least a portion of the logic elements, and programmable to route one or more signals from at least a portion of the logic elements to produce the one or more output signals via the output interface.